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From: Thomas Gleixner <tglx@linutronix.de>
To: K Prateek Nayak <kprateek.nayak@amd.com>,
	LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Tom Lendacky <thomas.lendacky@amd.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	Arjan van de Ven <arjan@linux.intel.com>,
	Huang Rui <ray.huang@amd.com>, Juergen Gross <jgross@suse.com>,
	Dimitri Sivanich <dimitri.sivanich@hpe.com>,
	Michael Kelley <mikelley@microsoft.com>,
	Wei Liu <wei.liu@kernel.org>, Pu Wen <puwen@hygon.cn>,
	Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
	Sohil Mehta <sohil.mehta@intel.com>,
	Gautham Shenoy <gautham.shenoy@amd.com>
Subject: Re: [patch V4 24/41] x86/cpu: Provide cpu_init/parse_topology()
Date: Mon, 28 Aug 2023 12:05:03 +0200	[thread overview]
Message-ID: <87r0nn8ots.ffs@tglx> (raw)
In-Reply-To: <934072fe-eca2-44df-94e7-9fed1dc8b502@amd.com>

Prateek!

On Mon, Aug 28 2023 at 11:37, K. Prateek Nayak wrote:
> On 8/14/2023 2:24 PM, Thomas Gleixner wrote:
>
> Since these enums come from the description of level type of CPUID leaf
> 0x1f, can we have a short description clarifying what each signify. This
> will also help clarify the mappings for AMD's extended CPUID leaf
> 0x80000026 (specifically for CCX and CCD level types). I had following
> in my mind:

Makes sense.

>  	TOPO_MODULE_DOMAIN,
> +	/*
> +	 * If exists, represents a group of tiles within
> +	 * an instance of the next domain
> +	 *
> +	 * On Intel: This level contains a group of Tile
> +	 * type as described by CPUID leaf 0x1f
> +	 *
> +	 * On AMD: This is the group of "Complex" type
> +	 * instances as described by CPUID leaf
> +	 * 0x8000_0026
> +	 */
>  	TOPO_TILE_DOMAIN,
> +	/*
> +	 * If exists, represents a group of dies within an
> +	 * instance of the next domain
> +	 *
> +	 * On Intel: This level contains group of Die
> +	 * type as described by CPUID leaf 0x1f
> +	 *
> +	 * On AMD: This is the group of "CCD (Die)"
> +	 * type instances as described by CPUID leaf
> +	 * 0x8000_0026
> +	 */
>  	TOPO_DIE_DOMAIN,
> +	/*
> +	 * If exists, represents a group of packages
> +	 * within the root domain
> +	 */
>  	TOPO_PKG_DOMAIN,
> +	/* Topmost domain with a singular instance */
>  	TOPO_ROOT_DOMAIN,
>  	TOPO_MAX_DOMAIN,
>  };

Now this begs the obvious question what the actual meaning of these
domains is and what's their relevance for the kernel.

It's probably undisputed what SMT/CORE mean and what their relevance is.
The PKG/DIE domains are pretty clear too.

Now we have:

    MODULE      (Intel only)

    TILE        Intel, AMD names it "Complex"

So here are the questions:

   - is TILE to "Complex" the proper mapping?

   - which information is conveyed by MODULE and TILE?

   - Are these really different between AMD and Intel or is this some
     naming convention issue which needs to be resolved?

Thanks,

        tglx


  reply	other threads:[~2023-08-28 10:05 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-14  8:53 [patch V4 00/41] x86/cpu: Rework the topology evaluation Thomas Gleixner
2023-08-14  8:53 ` [patch V4 01/41] x86/cpu/hygon: Fix the CPU topology evaluation for real Thomas Gleixner
2023-08-14  8:53 ` [patch V4 02/41] cpu/SMT: Make SMT control more robust against enumeration failures Thomas Gleixner
2023-08-15 21:15   ` Dave Hansen
2023-10-10 12:18     ` Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 03/41] x86/apic: Fake primary thread mask for XEN/PV Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 04/41] x86/cpu: Encapsulate topology information in cpuinfo_x86 Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 05/41] x86/cpu: Move phys_proc_id into topology info Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 06/41] x86/cpu: Move cpu_die_id " Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 07/41] scsi: lpfc: Use topology_core_id() Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 08/41] hwmon: (fam15h_power) " Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 09/41] x86/cpu: Move cpu_core_id into topology info Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 10/41] x86/cpu: Move cu_id " Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 11/41] x86/cpu: Remove pointless evaluation of x86_coreid_bits Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 12/41] x86/cpu: Move logical package and die IDs into topology info Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 13/41] x86/cpu: Move cpu_l[l2]c_id " Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 14/41] x86/apic: Use BAD_APICID consistently Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 15/41] x86/apic: Use u32 for APIC IDs in global data Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:53 ` [patch V4 16/41] x86/apic: Use u32 for check_apicid_used() Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:54 ` [patch V4 17/41] x86/apic: Use u32 for cpu_present_to_apicid() Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:54 ` [patch V4 18/41] x86/apic: Use u32 for phys_pkg_id() Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:54 ` [patch V4 19/41] x86/apic: Use u32 for [gs]et_apic_id() Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:54 ` [patch V4 20/41] x86/apic: Use u32 for wakeup_secondary_cpu[_64]() Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-10-13 10:32   ` [tip: x86/core] x86/apic, x86/hyperv: Use u32 in hv_snp_boot_ap() too tip-bot2 for Ingo Molnar
2023-08-14  8:54 ` [patch V4 21/41] x86/cpu/topology: Cure the abuse of cpuinfo for persisting logical ids Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:54 ` [patch V4 22/41] x86/cpu: Provide debug interface Thomas Gleixner
2023-10-13  9:38   ` [tip: x86/core] " tip-bot2 for Thomas Gleixner
2023-08-14  8:54 ` [patch V4 23/41] x86/cpu: Provide cpuid_read() et al Thomas Gleixner
2023-08-14  8:54 ` [patch V4 24/41] x86/cpu: Provide cpu_init/parse_topology() Thomas Gleixner
2023-08-28  6:07   ` K Prateek Nayak
2023-08-28 10:05     ` Thomas Gleixner [this message]
2023-08-28 14:03       ` Arjan van de Ven
2023-08-28 14:28       ` K Prateek Nayak
2023-08-28 14:34         ` Arjan van de Ven
2023-08-29  3:16           ` K Prateek Nayak
2023-09-15 11:54             ` Peter Zijlstra
2023-09-15 14:04               ` Arjan van de Ven
2023-09-19  3:54                 ` K Prateek Nayak
2023-09-19  8:13                   ` Thomas Gleixner
2023-09-20  3:23                     ` K Prateek Nayak
2023-09-19 13:44                   ` Arjan van de Ven
2023-09-20  3:21                     ` K Prateek Nayak
2023-09-14  9:20         ` K Prateek Nayak
2023-09-15 11:46           ` Thomas Gleixner
2023-08-14  8:54 ` [patch V4 25/41] x86/cpu: Add legacy topology parser Thomas Gleixner
2023-08-14  8:54 ` [patch V4 26/41] x86/cpu: Use common topology code for Centaur and Zhaoxin Thomas Gleixner
2023-08-14  8:54 ` [patch V4 27/41] x86/cpu: Move __max_die_per_package to common.c Thomas Gleixner
2023-08-14  8:54 ` [patch V4 28/41] x86/cpu: Provide a sane leaf 0xb/0x1f parser Thomas Gleixner
2023-08-16 12:09   ` Zhang, Rui
2023-08-17  9:11     ` Thomas Gleixner
2023-08-14  8:54 ` [patch V4 29/41] x86/cpu: Use common topology code for Intel Thomas Gleixner
2023-08-14  8:54 ` [patch V4 30/41] x86/cpu/amd: Provide a separate accessor for Node ID Thomas Gleixner
2023-08-14  8:54 ` [patch V4 31/41] x86/cpu: Provide an AMD/HYGON specific topology parser Thomas Gleixner
2023-08-14  8:54 ` [patch V4 32/41] x86/smpboot: Teach it about topo.amd_node_id Thomas Gleixner
2023-08-14  8:54 ` [patch V4 33/41] x86/cpu: Use common topology code for AMD Thomas Gleixner
2023-08-14  8:54 ` [patch V4 34/41] x86/cpu: Use common topology code for HYGON Thomas Gleixner
2023-08-14  8:54 ` [patch V4 35/41] x86/mm/numa: Use core domain size on AMD Thomas Gleixner
2023-08-14  8:54 ` [patch V4 36/41] x86/cpu: Make topology_amd_node_id() use the actual node info Thomas Gleixner
2023-08-14  8:54 ` [patch V4 37/41] x86/cpu: Remove topology.c Thomas Gleixner
2023-08-14  8:54 ` [patch V4 38/41] x86/cpu: Remove x86_coreid_bits Thomas Gleixner
2023-08-14  8:54 ` [patch V4 39/41] x86/apic: Remove unused phys_pkg_id() callback Thomas Gleixner
2023-08-14  8:54 ` [patch V4 40/41] x86/xen/smp_pv: Remove cpudata fiddling Thomas Gleixner
2023-08-14  8:54 ` [patch V4 41/41] x86/apic/uv: Remove the private leaf 0xb parser Thomas Gleixner
2023-08-14 14:36 ` [patch V4 00/41] x86/cpu: Rework the topology evaluation Peter Zijlstra
2023-08-16 11:36 ` Zhang, Rui

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