Re: [PATCH] x86/i8259: Work around buggy legacy PIC

Maximilian Luz
2021-05-14T11:58:56Z

On 5/14/21 9:41 PM, Sachi King wrote:
> On Thursday, May 13, 2021 8:36:27 PM AEST David Laight wrote:
>>> -----Original Message-----
>>> From: Maximilian Luz <luzmaximilian@gmail.com>
>>> Sent: 13 May 2021 11:12
>>> To: David Laight <David.Laight@ACULAB.COM>; Thomas Gleixner
>>> <tglx@linutronix.de>; Ingo Molnar <mingo@redhat.com>; Borislav Petkov
>>> <bp@alien8.de>
>>> Cc: H. Peter Anvin <hpa@zytor.com>; Sachi King <nakato@nakato.io>;
>>> x86@kernel.org; linux-kernel@vger.kernel.org; stable@vger.kernel.org
>>> Subject: Re: [PATCH] x86/i8259: Work around buggy legacy PIC
>>>
>>> On 5/13/21 10:10 AM, David Laight wrote:
>>>
>>>> From: Maximilian Luz
>>>>
>>>>> Sent: 12 May 2021 22:05
>>>>>
>>>>>
>>>>>
>>>>> The legacy PIC on the AMD variant of the Microsoft Surface Laptop 4
>>>>> has
>>>>> some problems on boot. For some reason it consistently does not
>>>>> respond
>>>>> on the first try, requiring a couple more tries before it finally
>>>>> responds.
>>>>
>>>>
>>>>
>>>> That seems very strange, something else must be going on that causes the
>>>> grief.
>>>> The 8259 will be built into to the one of the cpu support
>>>> chips.
>>>> I can't imagine that requires anything special.
>>>
>>>
>>> Right, it's definitely strange. Both Sachi (I imagine) and I don't know
>>> much about these devices, so we're open for suggestions.
>>
>>
>> I found a copy of the datasheet (I don't seem to have the black book):
>>
>> https://pdos.csail.mit.edu/6.828/2010/readings/hardware/8259A.pdf
>>
>> The PC hardware has two 8259 in cascade mode.
>> (Cascaded using an interrupt that wasn't really using in the original
>> 8088 PC which only had one 8259.)
>>
>> I wonder if the bios has actually initialised is properly.
>> Some initialisation writes have to be done to set everything up.
>
> I suspect by the displayed behaviour you are correct and that it has
> not. I'm struggling to figure out who to talk to to see that is
> something that can be fixed in the firmware.

I'd assume that _some_ sort of interrupt setup is done by the BIOS/UEFI.
The UEFI on those devices is fairly well-featured, with touch support
via SPI and all. Furthermore, keyboard (also supported in the device's
UEFI) is handled via a custom UART protocol. Unless they rely on polling
for all of that, I believe they'd have to set up some interrupts.

Although, as you mention later on, that could also be handled via the
IOAPIC and the PIC is actually not supposed to be used. Maybe some
legacy component that never got tested and just broke with some new
hardware/firmware revision without anyone noticing? And since Linux
still seems to rely on that, we might be the first to notice.

Regards,
Max