From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7231EC5519F for ; Sun, 22 Nov 2020 16:13:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BE9420781 for ; Sun, 22 Nov 2020 16:13:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="wbPgiX/x" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728041AbgKVQNL (ORCPT ); Sun, 22 Nov 2020 11:13:11 -0500 Received: from mail.kernel.org ([198.145.29.99]:48920 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727740AbgKVQNK (ORCPT ); Sun, 22 Nov 2020 11:13:10 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 337262076E; Sun, 22 Nov 2020 16:13:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1606061590; bh=dw6V/TaKwc/LLl0vFroSZOeUcr5KdGMp8TY0Va3U6eg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=wbPgiX/x3V2YUUKupJ7xnX2Rhc9iOJxM/GLyk+cK4iEOeT5Ptmy9eb/ApyxPkpFGq p9OOSq1TI4IA8mAlrepzocox+8Bd2R7MpbAkOubJirXVInpOk4Wrfg+wCaV2hSkQFx X2/1sbAUlrhQsQmBX7YKhkv/2GZ97A1aKIjl+kso= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1kgrzA-00CihO-5D; Sun, 22 Nov 2020 16:13:08 +0000 Date: Sun, 22 Nov 2020 16:13:07 +0000 Message-ID: <87r1olid4c.wl-maz@kernel.org> From: Marc Zyngier To: Thomas Gleixner Cc: LAK , linux-kernel , Will Deacon , Catalin Marinas , Valentin Schneider , Peter Zijlstra , Android Kernel Team , mark.rutland@arm.com Subject: Re: [PATCH 0/2] arm64: Allow the rescheduling IPI to bypass irq_enter/exit In-Reply-To: <87lfewnmdz.fsf@nanos.tec.linutronix.de> References: <20201101131430.257038-1-maz@kernel.org> <87ft5q18qs.fsf@nanos.tec.linutronix.de> <91cde5eeb22eb2926515dd27113c664a@kernel.org> <87lfewnmdz.fsf@nanos.tec.linutronix.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26.3 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, catalin.marinas@arm.com, Valentin.Schneider@arm.com, peterz@infradead.org, kernel-team@android.com, mark.rutland@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 20 Nov 2020 14:17:12 +0000, Thomas Gleixner wrote: Thomas, > So with the pre 5.8 scheduler IPI we had scheduler_ipi() doing wonderful > things [... tons of interesting and helpful stuff ...] > Hope that clarifies it. It does in a way, as it maps some of the low-level x86 things onto generic concepts. It certainly outlines that we have a lot of work ahead of us, none of which can be expected to be a quick fix. It requires restructuring a lot of the low-level arm64 code (Mark has been toying with it for a couple of years now), and rejig it in funny ways to match the expectations of the core code. I haven't tried to think about 32bit ARM just yet, and we may have to sever the IRQ ties that exist between the two architectures if we want to make forward progress in a reasonable time frame. In general, it looks that we'll need a new interface from the generic low-level IRQ entry code into this new common framework. > > If arm64 has forever been broken, I'd really like to know and fix it. > > Define broken. It kinda works with all the warts and bolts in tracing, > context tracking and other places. Is it entirely correct? Probably > not. > > The scheduler IPI is trivial compared to the more interesting ones like > NMI, MCE, breakpoint, debug exceptions etc. We found quite some > interesting issues with all of that muck during our 'noinstr' chase. Yup, point taken. However, given the complexity of the above and the fact that we currently have a measurable performance regression in 5.10, I'll respin the original series with the cleanups you mentioned, and the added note that we *really* need to sort this. Thanks, M. -- Without deviation from the norm, progress is not possible.