From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46C1B2749D7; Fri, 18 Apr 2025 13:10:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744981816; cv=none; b=RMpg7gABfFe3pEelFVIacxRI0Y6MC3hFdxjmJxpdm/CFGNziQ88K9CfyYMuRq1zCww3xfDoler+URg3f/N/Hw3FEo2JGCtMYuZq+vEmlgyqghIsFRAllKxYVNp0GyI9deTdAPDFqBXImQsUVoSqY/YB83SS4AIiPmuQ9xxcf7Jo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744981816; c=relaxed/simple; bh=LUwIz8oIu9xUE0rOVd4q9tz/WUXmYgPFjOKIDlZ74D8=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=OIO1TyWJFnCk+XOPdQcnMepgcfP0UnimE1Pzpg0u6BC37dTJJnTAjNGNCyXlZn3HnZh+sizB37rR91Vbk+dO+pewhePLD640EiyQ5/2eM+WuoALl12L1Z/Xo3pkbhilJkZ9+Yykm1PTCYRlmkQ92evQXmBg5s3f5B3gLkJBjsak= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WeBT0/vM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WeBT0/vM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5D56C4CEEB; Fri, 18 Apr 2025 13:10:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744981815; bh=LUwIz8oIu9xUE0rOVd4q9tz/WUXmYgPFjOKIDlZ74D8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=WeBT0/vMVbNcRplOOST+5Ywo6QdaFrdxfVR2LSNE6s00ZuWarFlBLjsZiH3HAyYKB tjSOHdewvgYfgveW4QcOuOuVyF9hllgu7PfauZirBRfnBvBM+jiWwXlgOKVwMIKS+Q GmfbgPKsrMXhQSbCta9B4CyBJce1bsWE+my0t9XFK+9AHIIZ/J4Z6vLfdZttpoturQ oqnBm7nat4DH6icCkWPPaVXGNTyvZ41kbftOXXmNjEExJLAant5gV+vnBUtirN2bmh +zAVEg/Tpibq1xySirpgzczkJByenekH4Ql+nAKFVnqKokjXPdouWyli9VCW27Ntxw fcSq4GfHkKtzw== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1u5lTx-006irK-6I; Fri, 18 Apr 2025 14:10:13 +0100 Date: Fri, 18 Apr 2025 14:10:19 +0100 Message-ID: <87sem5y5s4.wl-maz@kernel.org> From: Marc Zyngier To: Jiayuan Liang Cc: Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 0/1] KVM-arm: Optimize cache flush by only flushing on vcpu0 In-Reply-To: <20250418102244.2182975-1-ljykernel@163.com> References: <20250418102244.2182975-1-ljykernel@163.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ljykernel@163.com, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 18 Apr 2025 11:22:43 +0100, Jiayuan Liang wrote: > > This is an RFC patch to optimize cache flushing behavior in KVM/arm64. > > When toggling cache state in a multi-vCPU guest, we currently flush the VM's > stage2 page tables on every vCPU that transitions cache state. This leads to > redundant cache flushes during guest boot, as each vCPU performs the same > flush operation. > > In a typical guest boot sequence, vcpu0 is the first to enable caches, and > other vCPUs follow afterward. By the time secondary vCPUs enable their caches, > the flush performed by vcpu0 has already ensured cache coherency for the > entire VM. The most immediate issue I can spot is that vcpu0 is not special. There is nothing that says vcpu0 will be the first switching its MMU on, nor that vcpu0 will ever be running. I guess what you would want instead is that the *first* vcpu that enables its MMU performs the CMOs, while the others may not have to. But even then, this changes a behaviour some guests *may* be relying on, which is that what they have written while their MMU was off is visible with the MMU on, without the guest doing any CMO of its own. A lot of this stuff comes from the days where we were mostly running 32bit guests, some of which had (and still have) pretty bad assumptions (set/way operations being one of them). 64bit guests *should* be much better behaved, and I wonder whether we could actually drop the whole thing altogether for those. Something like the hack below. But this requires testing and more thought than I'm prepared to on a day off... ;-) Thanks, M. diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index bd020fc28aa9c..9d05e65433916 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -85,9 +85,11 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C * get set in SCTLR_EL1 such that we can detect when the guest * MMU gets turned on and do the necessary cache maintenance - * then. + * then. Limit this dance to 32bit guests, assuming that 64bit + * guests are reasonably behaved. */ - if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) + if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB) && + vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 |= HCR_TVM; } -- Jazz isn't dead. It just smells funny.