From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25136CE7A8A for ; Sun, 24 Sep 2023 14:48:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230136AbjIXOsr (ORCPT ); Sun, 24 Sep 2023 10:48:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230070AbjIXOsq (ORCPT ); Sun, 24 Sep 2023 10:48:46 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E59DFB for ; Sun, 24 Sep 2023 07:48:40 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32B1BC433C7; Sun, 24 Sep 2023 14:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695566920; bh=5wwQymIM9y0KKXNvNJLppJrlGUb4t1sAROPS7agfkPc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=cB7nBRYxoQEcOuEzX2MFVO4aH9E2xJU/UztZrurs5gb6lfk6vH19Pi6chl6oSO1fc gUtruyY9zejUyaMrM/Jv7mbVHB+zGK1WCUmM0Q+FHKQQKuvIhCMFLQIgOnzajwc46Z fj+081NSxWnVGI/teLzqhrghCu4L+xFehJzjEH/yx4CNlunQKAYBecJptBoVv0Uwyg QQq4h+1i/rM74zxvwuGUf8cI+k+Hdhzn8sNSsNtkB1/4dveHJeg+ChfJQCPhjUkql7 wUXN9p/AdJDCqlOPzCZ2eRQzA+nF2u1BixE0Gtm/eHQ/gBwyjeH+atod755ufJW2HU mH8giEIxTtNlQ== Received: from [85.255.234.76] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qkQPV-00FiVl-MD; Sun, 24 Sep 2023 15:48:37 +0100 Date: Sun, 24 Sep 2023 15:48:36 +0100 Message-ID: <87sf734ofv.wl-maz@kernel.org> From: Marc Zyngier To: Kristina Martsenko Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Vladimir Murzin , Colton Lewis , linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] KVM: arm64: Add handler for MOPS exceptions In-Reply-To: <20230922112508.1774352-2-kristina.martsenko@arm.com> References: <20230922112508.1774352-1-kristina.martsenko@arm.com> <20230922112508.1774352-2-kristina.martsenko@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 85.255.234.76 X-SA-Exim-Rcpt-To: kristina.martsenko@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, vladimir.murzin@arm.com, coltonlewis@google.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Kristina, On Fri, 22 Sep 2023 12:25:07 +0100, Kristina Martsenko wrote: > > An Armv8.8 FEAT_MOPS main or epilogue instruction will take an exception > if executed on a CPU with a different MOPS implementation option (A or > B) than the CPU where the preceding prologue instruction ran. In this > case the OS exception handler is expected to reset the registers and > restart execution from the prologue instruction. > > A KVM guest may use the instructions at EL1 at times when the guest is > not able to handle the exception, expecting that the instructions will > only run on one CPU (e.g. when running UEFI boot services in the guest). > As KVM may reschedule the guest between different types of CPUs at any > time (on an asymmetric system), it needs to also handle the resulting > exception itself in case the guest is not able to. A similar situation > will also occur in the future when live migrating a guest from one type > of CPU to another. > > Add handling for the MOPS exception to KVM. The handling can be shared > with the EL0 exception handler, as the logic and register layouts are > the same. The exception can be handled right after exiting a guest, > which avoids the cost of returning to the host exit handler. > > Similarly to the EL0 exception handler, in case the main or epilogue > instruction is being single stepped, it makes sense to finish the step > before executing the prologue instruction, so advance the single step > state machine. What is the rationale for advancing the state machine? Shouldn't we instead return to the guest and immediately get the SS exception, which in turn gets reported to userspace? Is it because we rollback the PC to a previous instruction? In the latter case, won't userspace see multiple SS exceptions for the middle instruction if trapping from the epilogue? This would be a bit surprising, to say the least. Thanks, M. -- Without deviation from the norm, progress is not possible.