From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62706C001B0 for ; Thu, 10 Aug 2023 14:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235433AbjHJOMr (ORCPT ); Thu, 10 Aug 2023 10:12:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232960AbjHJOMp (ORCPT ); Thu, 10 Aug 2023 10:12:45 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 695DA1B4 for ; Thu, 10 Aug 2023 07:12:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691676765; x=1723212765; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version:content-transfer-encoding; bh=bdIIOTKh7IfFQ6pXhNlODCj7FRjKYScx0QSb05B/Zzw=; b=naxYDxm6LubqtWl28vughBNBF3Uc3fokwgJPbPJSlHV9T+enGkHDgkUj Y7Hzx+Gs2fJ5HjqpTeCVR9KiC2kgOejYBqhj8gbjQUZaGru18JnZw8ICO FPf+bgnXGTwajU38vkFeJwTHj4waO2uHP/+MhsjkokrUAdeWddVFSuImR ex/9ycYIZ8GxYSoTDs6WsxesDpevjnUImAKVOhqs38zRJdDJygm+6Wtvl FOqWEbIBpK+vkdO40BZoSi/Ux5dasG5TXgDTyjMNei7CueBDF2YVGAmKl ACT0MhP4eUssFzuV6utgZELwMacuptZtjhyHGuQqsJVGDsj6ZTHk8c1tk A==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="356373934" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="356373934" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 07:12:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="846410883" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="846410883" Received: from jnikula-mobl4.fi.intel.com (HELO localhost) ([10.237.66.162]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 07:12:34 -0700 From: Jani Nikula To: Wang Jinchao , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: stone.xulei@xfusion.com Subject: Re: [PATCH] drm/i915/gmch: fix build error var set but not used In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: Date: Thu, 10 Aug 2023 17:12:31 +0300 Message-ID: <87sf8rq94g.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 10 Aug 2023, Wang Jinchao wrote: > When CONFIG_PNP is not defined, i915 will fail to compile with error bell= ow: > drivers/gpu/drm/i915/soc/intel_gmch.c:43:13: error: variable =E2=80=98mc= hbar_addr=E2=80=99 set but not used > Fix it by surrounding variable declaration and assignment with ifdef > > Signed-off-by: Wang Jinchao Thanks for the patch, but this was fixed a couple of months ago by commit b02a9a0c6cb3 ("drm/i915/gmch: avoid unused variable warning"). Please check the development trees or linux-next before sending fixes. Thanks, Jani. > --- > drivers/gpu/drm/i915/soc/intel_gmch.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/soc/intel_gmch.c b/drivers/gpu/drm/i915= /soc/intel_gmch.c > index 6d0204942f7a..d2c442b0b4eb 100644 > --- a/drivers/gpu/drm/i915/soc/intel_gmch.c > +++ b/drivers/gpu/drm/i915/soc/intel_gmch.c > @@ -38,16 +38,17 @@ intel_alloc_mchbar_resource(struct drm_i915_private *= i915) > { > int reg =3D GRAPHICS_VER(i915) >=3D 4 ? MCHBAR_I965 : MCHBAR_I915; > u32 temp_lo, temp_hi =3D 0; > - u64 mchbar_addr; > int ret; > - > +#ifdef CONFIG_PNP > + u64 mchbar_addr; > +#endif > if (GRAPHICS_VER(i915) >=3D 4) > pci_read_config_dword(i915->gmch.pdev, reg + 4, &temp_hi); > pci_read_config_dword(i915->gmch.pdev, reg, &temp_lo); > - mchbar_addr =3D ((u64)temp_hi << 32) | temp_lo; >=20=20 > /* If ACPI doesn't have it, assume we need to allocate it ourselves */ > #ifdef CONFIG_PNP > + mchbar_addr =3D ((u64)temp_hi << 32) | temp_lo; > if (mchbar_addr && > pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) > return 0; --=20 Jani Nikula, Intel Open Source Graphics Center