From: Marc Zyngier <maz@kernel.org>
To: Jianmin Lv <lvjianmin@loongson.cn>
Cc: Robert Moore <robert.moore@intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org, loongarch@lists.linux.dev,
Hanjun Guo <guohanjun@huawei.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@loongson.cn>
Subject: Re: [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support
Date: Mon, 18 Jul 2022 14:26:31 +0100 [thread overview]
Message-ID: <87sfmyzh4o.wl-maz@kernel.org> (raw)
In-Reply-To: <7ed06824-4ccb-a9c4-fa01-583006ab90c1@loongson.cn>
On Mon, 18 Jul 2022 13:28:11 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/17 上午2:10, Marc Zyngier wrote:
> > [+ Robert Moore]
> >
> > On Fri, 15 Jul 2022 08:05:37 +0100,
> > Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>
> >> From: Huacai Chen <chenhuacai@loongson.cn>
> >>
> >> LoongArch-specific interrupt controllers (similar to APIC) are added
> >> in the next revision of ACPI Specification (current revision is 6.4),
> >> which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
> >> HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
> >> (PCHMSI). This patch add their definition.
> >>
> >> ACPI changes of LoongArch-specific interrupt controllers have already
> >> been approved in the ECRs, and will be public in the next revision of
> >> ACPI Specification.
> >>
> >> Reference: https://mantis.uefi.org/mantis/view.php?id=2203
> >> Reference: https://mantis.uefi.org/mantis/view.php?id=2313
> >>
> >> Above links needs login(available for ASWG), so the following link(
> >> the ECR file for adding LoongArch APICs into ACPI spec) is provided
> >> for public:
> >>
> >> https://github.com/lvjianmin-loongson/acpica/blob/master/Add%20APIC%20Structures%20for%20Loongarch%20in%20MADT-rev3.pdf
> >>
> >> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> >> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> >
> > Since the ACPI maintainers are unwilling to take this patch (for
> > undisclosed reasons), we need something to unblock this sorry
> > situation, as I don't think it is fair on the LoongArch folks to be
> > blocked for another cycle on this ground only.
> >
> > I'm proposing to replace this patch with the following, which will
> > allow the patches to be merged without breaking anything. Once the
> > ACPI support is updated, we'll be able to simply revert this patch.
> >
> > Thanks,
> >
> > M.
> >
> > From 43ec25d2dbde3c422cce430c9d5ec32fbe7b255c Mon Sep 17 00:00:00 2001
> > From: Marc Zyngier <maz@kernel.org>
> > Date: Sat, 16 Jul 2022 18:56:10 +0100
> > Subject: [PATCH] LoongArch: Provisionally add ACPICA data structures
> >
> > The LoongArch architecture is using ACPI, but the spec containing
> > the required updates still is in an unreleased state.
> >
> > Instead of preventing the inclusion of the IRQ support into the
> > kernel, add the missing bits to the arch-specific parts of
> > the ACPICA support.
> >
> > Once the ACPICA bits are updated to the version that supports
> > LoongArch, these bits can eventually be removed.
> >
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > ---
> > arch/loongarch/include/asm/acpi.h | 138 ++++++++++++++++++++++++++++++
> > 1 file changed, 138 insertions(+)
> >
> > diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h
> > index 62044cd5b7bc..6155e46098af 100644
> > --- a/arch/loongarch/include/asm/acpi.h
> > +++ b/arch/loongarch/include/asm/acpi.h
> > @@ -31,6 +31,144 @@ static inline bool acpi_has_cpu_in_madt(void)
> > extern struct list_head acpi_wakeup_device_list;
> > +/*
> > + * Temporary definitions until the core ACPICA code gets updated (see
> > + * 1656837932-18257-1-git-send-email-lvjianmin@loongson.cn and its
> > + * follow-ups for the "rationale").
> > + *
> > + * Once the "legal reasons" are cleared and that the code is merged,
> > + * this can be dropped entierely.
> > + */
> > +#if (ACPI_CA_VERSION == 0x20220331 && !defined(LOONGARCH_ACPICA_EXT))
> > +
> > +#define LOONGARCH_ACPICA_EXT 1
> > +
> > +#define ACPI_MADT_TYPE_CORE_PIC 17
> > +#define ACPI_MADT_TYPE_LIO_PIC 18
> > +#define ACPI_MADT_TYPE_HT_PIC 19
> > +#define ACPI_MADT_TYPE_EIO_PIC 20
> > +#define ACPI_MADT_TYPE_MSI_PIC 21
> > +#define ACPI_MADT_TYPE_BIO_PIC 22
> > +#define ACPI_MADT_TYPE_LPC_PIC 23
> > +
> > +/* Values for Version field above */
> > +
> > +enum acpi_madt_core_pic_version {
> > + ACPI_MADT_CORE_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_CORE_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_lio_pic_version {
> > + ACPI_MADT_LIO_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_LIO_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_eio_pic_version {
> > + ACPI_MADT_EIO_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_EIO_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_ht_pic_version {
> > + ACPI_MADT_HT_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_HT_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_HT_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_bio_pic_version {
> > + ACPI_MADT_BIO_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_BIO_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_msi_pic_version {
> > + ACPI_MADT_MSI_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_MSI_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
> > +enum acpi_madt_lpc_pic_version {
> > + ACPI_MADT_LPC_PIC_VERSION_NONE = 0,
> > + ACPI_MADT_LPC_PIC_VERSION_V1 = 1,
> > + ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
> > +};
> > +
>
> Hi, Marc, I add #pragma here to make following structures align to 1
> byte as include/acpi/actbl2.h, or else, the MADT will not be parsed
> correctly.
If that's required, please add it.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-07-18 13:26 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support Jianmin Lv
2022-07-16 18:10 ` Marc Zyngier
2022-07-17 1:05 ` Jianmin Lv
2022-07-18 12:28 ` Jianmin Lv
2022-07-18 13:26 ` Marc Zyngier [this message]
2022-07-15 7:05 ` [PATCH V15 02/15] APCI: irq: Add support for multiple GSI domains Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 04/15] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 05/15] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 06/15] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 07/15] irqchip: remove COMPILE_TEST for pch-pic and pch-msi Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 08/15] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 09/15] irqchip/loongson-pch-msi: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 10/15] irqchip/loongson-htvec: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 11/15] irqchip/loongson-liointc: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 12/15] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 13/15] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 14/15] irqchip: Add LoongArch CPU " Jianmin Lv
2022-07-15 15:11 ` Huacai Chen
2022-07-17 12:02 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 15/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
2022-07-16 18:39 ` [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Marc Zyngier
2022-07-17 1:06 ` Jianmin Lv
2022-07-17 10:02 ` Marc Zyngier
2022-07-17 11:29 ` Jianmin Lv
2022-07-17 14:08 ` Huacai Chen
2022-07-17 14:43 ` Marc Zyngier
2022-07-18 2:38 ` Huacai Chen
2022-07-18 6:43 ` Marc Zyngier
2022-07-18 8:35 ` Huacai Chen
2022-07-17 14:49 ` Marc Zyngier
2022-07-18 1:07 ` Jianmin Lv
2022-07-18 6:39 ` Marc Zyngier
2022-07-18 8:29 ` Jianmin Lv
2022-07-18 8:39 ` Huacai Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87sfmyzh4o.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=chenhuacai@loongson.cn \
--cc=guohanjun@huawei.com \
--cc=jiaxun.yang@flygoat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=loongarch@lists.linux.dev \
--cc=lorenzo.pieralisi@arm.com \
--cc=lvjianmin@loongson.cn \
--cc=robert.moore@intel.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox