From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A565C433EF for ; Mon, 18 Jul 2022 13:26:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234636AbiGRN0o (ORCPT ); Mon, 18 Jul 2022 09:26:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235428AbiGRN0i (ORCPT ); Mon, 18 Jul 2022 09:26:38 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B437298 for ; Mon, 18 Jul 2022 06:26:37 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id DA5C9B815E8 for ; Mon, 18 Jul 2022 13:26:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95A9CC341C0; Mon, 18 Jul 2022 13:26:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658150794; bh=4tiO4PApBXbBzVqE/dLoJLfQkxM8y4vZA0drfXcfE7g=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=HV2Fn4G5sZhal83TZdtyoJTVZ7a2oFLDCJAw6ZMpE0DbCQGPu1tza5qi2CX0FxfpH hpGYjlwArua1Zxlfg6SB5k1Pbmu1GShhkXXmfn8ryHDa6wTUpsYFB2bULowFSxMlgN L3ySt3eeE3AirkyCxj/sJOBKO/rvP5cOgOidiicKZ1iKOIp3zvA009Szw5Cbj/2DwV XqJ5kE5CQt6090/FpHmSSoSuMxWtBbKKzCHbQN0of0IImEY3HEHcdT/I+2Ia8gv6FP tqDqzCoMgXX0swYh14zmRTuNotwCgDDcDC3dn7fH30dX4n2bwBtcBTFWbQ6BNueJin 3bDVXKz/E3Hcg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oDQlc-008DVV-BW; Mon, 18 Jul 2022 14:26:32 +0100 Date: Mon, 18 Jul 2022 14:26:31 +0100 Message-ID: <87sfmyzh4o.wl-maz@kernel.org> From: Marc Zyngier To: Jianmin Lv Cc: Robert Moore , Thomas Gleixner , linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Hanjun Guo , Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen Subject: Re: [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support In-Reply-To: <7ed06824-4ccb-a9c4-fa01-583006ab90c1@loongson.cn> References: <1657868751-30444-1-git-send-email-lvjianmin@loongson.cn> <1657868751-30444-2-git-send-email-lvjianmin@loongson.cn> <87mtd93p3n.wl-maz@kernel.org> <7ed06824-4ccb-a9c4-fa01-583006ab90c1@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lvjianmin@loongson.cn, robert.moore@intel.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, guohanjun@huawei.com, lorenzo.pieralisi@arm.com, jiaxun.yang@flygoat.com, chenhuacai@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 18 Jul 2022 13:28:11 +0100, Jianmin Lv wrote: >=20 >=20 >=20 > On 2022/7/17 =E4=B8=8A=E5=8D=882:10, Marc Zyngier wrote: > > [+ Robert Moore] > >=20 > > On Fri, 15 Jul 2022 08:05:37 +0100, > > Jianmin Lv wrote: > >>=20 > >> From: Huacai Chen > >>=20 > >> LoongArch-specific interrupt controllers (similar to APIC) are added > >> in the next revision of ACPI Specification (current revision is 6.4), > >> which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINT= C), > >> HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC > >> (PCHMSI). This patch add their definition. > >>=20 > >> ACPI changes of LoongArch-specific interrupt controllers have already > >> been approved in the ECRs, and will be public in the next revision of > >> ACPI Specification. > >>=20 > >> Reference: https://mantis.uefi.org/mantis/view.php?id=3D2203 > >> Reference: https://mantis.uefi.org/mantis/view.php?id=3D2313 > >>=20 > >> Above links needs login(available for ASWG), so the following link( > >> the ECR file for adding LoongArch APICs into ACPI spec) is provided > >> for public: > >>=20 > >> https://github.com/lvjianmin-loongson/acpica/blob/master/Add%20APIC%20= Structures%20for%20Loongarch%20in%20MADT-rev3.pdf > >>=20 > >> Signed-off-by: Jianmin Lv > >> Signed-off-by: Huacai Chen > >=20 > > Since the ACPI maintainers are unwilling to take this patch (for > > undisclosed reasons), we need something to unblock this sorry > > situation, as I don't think it is fair on the LoongArch folks to be > > blocked for another cycle on this ground only. > >=20 > > I'm proposing to replace this patch with the following, which will > > allow the patches to be merged without breaking anything. Once the > > ACPI support is updated, we'll be able to simply revert this patch. > >=20 > > Thanks, > >=20 > > M. > >=20 > > From 43ec25d2dbde3c422cce430c9d5ec32fbe7b255c Mon Sep 17 00:00:00 2001 > > From: Marc Zyngier > > Date: Sat, 16 Jul 2022 18:56:10 +0100 > > Subject: [PATCH] LoongArch: Provisionally add ACPICA data structures > >=20 > > The LoongArch architecture is using ACPI, but the spec containing > > the required updates still is in an unreleased state. > >=20 > > Instead of preventing the inclusion of the IRQ support into the > > kernel, add the missing bits to the arch-specific parts of > > the ACPICA support. > >=20 > > Once the ACPICA bits are updated to the version that supports > > LoongArch, these bits can eventually be removed. > >=20 > > Signed-off-by: Marc Zyngier > > --- > > arch/loongarch/include/asm/acpi.h | 138 ++++++++++++++++++++++++++++++ > > 1 file changed, 138 insertions(+) > >=20 > > diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include= /asm/acpi.h > > index 62044cd5b7bc..6155e46098af 100644 > > --- a/arch/loongarch/include/asm/acpi.h > > +++ b/arch/loongarch/include/asm/acpi.h > > @@ -31,6 +31,144 @@ static inline bool acpi_has_cpu_in_madt(void) > > extern struct list_head acpi_wakeup_device_list; > > +/* > > + * Temporary definitions until the core ACPICA code gets updated (see > > + * 1656837932-18257-1-git-send-email-lvjianmin@loongson.cn and its > > + * follow-ups for the "rationale"). > > + * > > + * Once the "legal reasons" are cleared and that the code is merged, > > + * this can be dropped entierely. > > + */ > > +#if (ACPI_CA_VERSION =3D=3D 0x20220331 && !defined(LOONGARCH_ACPICA_EX= T)) > > + > > +#define LOONGARCH_ACPICA_EXT 1 > > + > > +#define ACPI_MADT_TYPE_CORE_PIC 17 > > +#define ACPI_MADT_TYPE_LIO_PIC 18 > > +#define ACPI_MADT_TYPE_HT_PIC 19 > > +#define ACPI_MADT_TYPE_EIO_PIC 20 > > +#define ACPI_MADT_TYPE_MSI_PIC 21 > > +#define ACPI_MADT_TYPE_BIO_PIC 22 > > +#define ACPI_MADT_TYPE_LPC_PIC 23 > > + > > +/* Values for Version field above */ > > + > > +enum acpi_madt_core_pic_version { > > + ACPI_MADT_CORE_PIC_VERSION_NONE =3D 0, > > + ACPI_MADT_CORE_PIC_VERSION_V1 =3D 1, > > + ACPI_MADT_CORE_PIC_VERSION_RESERVED =3D 2 /* 2 and greater are reserv= ed */ > > +}; > > + > > +enum acpi_madt_lio_pic_version { > > + ACPI_MADT_LIO_PIC_VERSION_NONE =3D 0, > > + ACPI_MADT_LIO_PIC_VERSION_V1 =3D 1, > > + ACPI_MADT_LIO_PIC_VERSION_RESERVED =3D 2 /* 2 and greater are reserve= d */ > > +}; > > + > > +enum acpi_madt_eio_pic_version { > > + ACPI_MADT_EIO_PIC_VERSION_NONE =3D 0, > > + ACPI_MADT_EIO_PIC_VERSION_V1 =3D 1, > > + ACPI_MADT_EIO_PIC_VERSION_RESERVED =3D 2 /* 2 and greater are reserve= d */ > > +}; > > + > > +enum acpi_madt_ht_pic_version { > > + ACPI_MADT_HT_PIC_VERSION_NONE =3D 0, > > + ACPI_MADT_HT_PIC_VERSION_V1 =3D 1, > > + ACPI_MADT_HT_PIC_VERSION_RESERVED =3D 2 /* 2 and greater are reserved= */ > > +}; > > + > > +enum acpi_madt_bio_pic_version { > > + ACPI_MADT_BIO_PIC_VERSION_NONE =3D 0, > > + ACPI_MADT_BIO_PIC_VERSION_V1 =3D 1, > > + ACPI_MADT_BIO_PIC_VERSION_RESERVED =3D 2 /* 2 and greater are reserve= d */ > > +}; > > + > > +enum acpi_madt_msi_pic_version { > > + ACPI_MADT_MSI_PIC_VERSION_NONE =3D 0, > > + ACPI_MADT_MSI_PIC_VERSION_V1 =3D 1, > > + ACPI_MADT_MSI_PIC_VERSION_RESERVED =3D 2 /* 2 and greater are reserve= d */ > > +}; > > + > > +enum acpi_madt_lpc_pic_version { > > + ACPI_MADT_LPC_PIC_VERSION_NONE =3D 0, > > + ACPI_MADT_LPC_PIC_VERSION_V1 =3D 1, > > + ACPI_MADT_LPC_PIC_VERSION_RESERVED =3D 2 /* 2 and greater are reserve= d */ > > +}; > > + >=20 > Hi, Marc, I add #pragma here to make following structures align to 1 > byte as include/acpi/actbl2.h, or else, the MADT will not be parsed > correctly. If that's required, please add it. Thanks, M. --=20 Without deviation from the norm, progress is not possible.