From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19A19C3F68F for ; Fri, 17 Jan 2020 17:11:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E3B962082F for ; Fri, 17 Jan 2020 17:11:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727519AbgAQRL3 (ORCPT ); Fri, 17 Jan 2020 12:11:29 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:56953 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726603AbgAQRL2 (ORCPT ); Fri, 17 Jan 2020 12:11:28 -0500 Received: from p5b06da22.dip0.t-ipconnect.de ([91.6.218.34] helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1isV9Y-0004lB-CS; Fri, 17 Jan 2020 18:11:24 +0100 Received: by nanos.tec.linutronix.de (Postfix, from userid 1000) id A2C70100C19; Fri, 17 Jan 2020 18:11:23 +0100 (CET) From: Thomas Gleixner To: Ramon Fried Cc: hkallweit1@gmail.com, Bjorn Helgaas , maz@kernel.org, lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: MSI irqchip configured as IRQCHIP_ONESHOT_SAFE causes spurious IRQs In-Reply-To: References: <87wo9ub5f6.fsf@nanos.tec.linutronix.de> <87imldbqe3.fsf@nanos.tec.linutronix.de> <87v9pcw55q.fsf@nanos.tec.linutronix.de> <87pnfjwxtx.fsf@nanos.tec.linutronix.de> <87zhem172r.fsf@nanos.tec.linutronix.de> Date: Fri, 17 Jan 2020 18:11:23 +0100 Message-ID: <87sgke1004.fsf@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Ramon, Ramon Fried writes: > On Fri, Jan 17, 2020 at 4:38 PM Thomas Gleixner wrote: >> This is wrong. MSI is edge type, not level and you are really mixing up >> the concepts here. >> >> The fact that the MSI block raises a level interrupt on the output side >> has absolutely nothing to do with the type of the MSI interrupt itself. >> >> MSI is edge type by definition and this does not change just because >> there is a translation unit between the MSI interrupt and the CPU >> controller. >> >> The actual MSI interrupts do not even know about the existance of that >> MSI block at all. They do not care, as all they need to know is a >> message and an address. When an interrupt is raised in the device the >> MSI chip associated to the device (PCI or something else) writes this >> message to the address exactly ONCE. And this exactly ONCE defines the >> edge nature of MSI. > > OK, now I understand my mistake. thanks. :) >> A proper designed MSI device should not send another message before the >> interrupt handler which is associated to the device has handled the >> interrupt at the device level. > > By "MSI device" you mean the MSI controller in the SOC or the endpoint > that sends the MSI ? The device which incorporates the MSI endpoint. Thanks, tglx