From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE672304976 for ; Wed, 3 Jun 2026 16:02:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780502561; cv=none; b=GzWwN2WT/EcI97hEwRgnCT0/+notZh4WmVL6Uq32FSEIj5GZ3nhB70tKq1dW1APLd811KJtqpP+j21mTfuIfU/dxCcyACo2mjKUrnXM/Gcb8aigx7p2+vZnLeSkDfScJlVUgR0e6h7te/PdUWKsgtAcXRxCViQfoBhefmqyyTWo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780502561; c=relaxed/simple; bh=JjqN4OdoQ2v818d+UOvGIpmftpjn02s/sHSgL8HIVxU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=st6PJeJeDSrbH+or1BlcXVKHAEaSnfIHImjBsXt7fvjXeLKo2OVPDfkGyutdqCZu5vLrTIEY+vhLgGV2a3FQliKIEFLWmE3D29jnYf1Ljw3xo8Meo/NwvYdM2ENeNyxzgOw8KIbMZU/w7NX28k7Ce1xys7LQ53Vg8NX7LLuTCKg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UUZCyM2l; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UUZCyM2l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B491B1F00893; Wed, 3 Jun 2026 16:02:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780502560; bh=2NyrIsagqNn/jHidzGig/bgO693GtobZSqwiUEMZ6Ls=; h=From:To:Cc:Subject:In-Reply-To:References:Date; b=UUZCyM2lNqVC8yhkZ2tgrN4iSNddj6KI/Dga362AOpKZ5G8QiM2R+6z8R21U5Vsjc Wl/1MBVCZ35+HQFl6aCIsjKyGN75JLNx5wfgCJXf7xxWUKf0sNJADVG1RrTofeZJtr nq6SFrXoDtBHBqD1Hmql5tMz/z8hmEebueV8v/mq7MwOY6Z/iD4AKSK0C1fXsQUbZX JtoMtLu3mvb7ZHIKg7m1EeNM8vf7x+8NmN+s39H8CqTol374aHQwQxAX9vXJdZbwI2 mzSIjcCu2gaHEknB5fQm8IpcefDR28ogqyPCPs/TYSuVLZyYt1g38EzpbymNvc0biK oUtQh7sz4/Ilg== From: Thomas Gleixner To: Markus Stockhausen , linux-kernel@vger.kernel.org Cc: Markus Stockhausen Subject: Re: [PATCH 2/2] irqchip/irq-realtek-rtl: Add multicore support In-Reply-To: <20260512184646.1896480-3-markus.stockhausen@gmx.de> References: <20260512184646.1896480-1-markus.stockhausen@gmx.de> <20260512184646.1896480-3-markus.stockhausen@gmx.de> Date: Wed, 03 Jun 2026 18:02:37 +0200 Message-ID: <87tsrj628y.ffs@fw13> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, May 12 2026 at 20:46, Markus Stockhausen wrote: > The Realtek IRQ driver currently supports only single core s/IRQ/interrupt/g > systems. So the higher end devices like RTL839x and RTL930x > with dual VPEs must be driven with NR_CPU=1. Enhance the > driver to support multicore (dual VPE) systems. For this: > > - Extend the register map for multiple cores > - Search for multiple CPU cores in the devicetree > - Improve the register helpers to support multiple cores > - Add an affinity setter > - Enhance the IRQ handler for multiple cores > > > -static inline void enable_gimr(int hw_irq) > +static inline void enable_gimr(int cpu, int hw_irq) unsigned int cpu - All over the place. > { > u32 gimr; > > - gimr = readl(REG(RTL_ICTL_GIMR)); > + gimr = readl(REG(cpu, RTL_ICTL_GIMR)); > gimr |= BIT(hw_irq); > - writel(gimr, REG(RTL_ICTL_GIMR)); > + writel(gimr, REG(cpu, RTL_ICTL_GIMR)); > } > > -static inline void disable_gimr(int hwirq) > +static inline void disable_gimr(int cpu, int hwirq) > { > u32 gimr; > > - gimr = readl(REG(RTL_ICTL_GIMR)); > + gimr = readl(REG(cpu, RTL_ICTL_GIMR)); > gimr &= ~BIT(hwirq); > - writel(gimr, REG(RTL_ICTL_GIMR)); > + writel(gimr, REG(cpu, RTL_ICTL_GIMR)); > } > > -static void write_irr(int hw_irq, u32 value) > +static void write_irr(int cpu, int hw_irq, u32 value) > { > - void __iomem *irr0 = REG(RTL_ICTL_IRR0); > + void __iomem *irr0 = REG(cpu, RTL_ICTL_IRR0); > unsigned int offset = IRR_OFFSET(hw_irq); > unsigned int shift = IRR_SHIFT(hw_irq); > u32 irr; > @@ -70,35 +71,73 @@ static void write_irr(int hw_irq, u32 value) > static void realtek_ictl_unmask_irq(struct irq_data *i) > { > unsigned long flags; > + cpumask_t cpus; > + int cpu; > + > + cpumask_and(&cpus, &realtek_ictl_cpu_configurable, > + irq_data_get_effective_affinity_mask(i)); What is this cpumask_and() for? The affinity setter already ensures that the effective mask is a subset of configurable, no? > > +static int realtek_ictl_irq_affinity(struct irq_data *i, > + const struct cpumask *dest, > + bool force) Please use the full 100 characters. > +{ > + cpumask_t cpu_configure; > + cpumask_t cpu_disable; > + cpumask_t cpu_enable; https://docs.kernel.org/process/maintainer-tip.html#variable-declarations > + unsigned long flags; > + int cpu; > + > + cpumask_and(&cpu_configure, cpu_present_mask, &realtek_ictl_cpu_configurable); > + cpumask_and(&cpu_enable, &cpu_configure, dest); > + cpumask_andnot(&cpu_disable, &cpu_configure, dest); > + > + raw_spin_lock_irqsave(&irq_lock, flags); scoped_guard(raw_spinlock, ....) { > + for_each_cpu(cpu, &cpu_disable) > + disable_gimr(cpu, i->hwirq); > + for_each_cpu(cpu, &cpu_enable) > + if (!irqd_irq_masked(i)) > + enable_gimr(cpu, i->hwirq); See bracket rules in the documentation I linked to. } > + raw_spin_unlock_irqrestore(&irq_lock, flags); > + > + irq_data_update_effective_affinity(i, &cpu_enable); > + > + return IRQ_SET_MASK_OK; > +} > + > static struct irq_chip realtek_ictl_irq = { > .name = "realtek-rtl-intc", > .irq_mask = realtek_ictl_mask_irq, > .irq_unmask = realtek_ictl_unmask_irq, > + .irq_set_affinity = realtek_ictl_irq_affinity, Please fix up the struct initializer according to documentation. Thanks, tglx