From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DCA4372EF2; Fri, 20 Mar 2026 08:24:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773995099; cv=none; b=Z8VO1ZH4JFb9K3BoL5q18p5l+huPLh+PPk1NaPE6WZR0L+Sq3iD65r7lmEC8WOiuSl6vJl+AIualQeEdHnocKGCL3tjke/gLlt6B1XgzvP0L1idmQKwpV83iljQ181EwYePRxPoAbwqsbMsorswzCnN3kGLgzhOMFgwoB9/ftjE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773995099; c=relaxed/simple; bh=5sQNvmWQfpu+8Hr47TI2X8prZ8bvsa2R1XHx8VD2x8U=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=CgVKyZjvbFIubV87D2n4rNHztaCvpXG1vBQCJZEt4+YrPaPMdQhMP4JBkwkh9ocxnbIRs5IKaXYeI6evnC89oQIBfN11TB3beLFAsOhOWTBdQSVrbczSxLL3qeVJ7KeAElkX5ZAlqULooFmEg+SOjrRipaWI+oxHUQ1EUu8jP94= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CzS5eoM0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CzS5eoM0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7FE54C2BC87; Fri, 20 Mar 2026 08:24:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773995099; bh=5sQNvmWQfpu+8Hr47TI2X8prZ8bvsa2R1XHx8VD2x8U=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=CzS5eoM0f2loHEf3GLYkghCyVQ2yYnMGqfDIRbO7GCqBNLBsQ20/Qo2IFO//yQjkP L96R3cHLc0svMwur92gnB0/OMaBzF3mSeJdJp4zo5wqxfI9egzkjCXOs6lPnRexoGt CGNUxpBADXLcD31k7tJNxqHxKv76QzAl1ebIPfaFSTVTR8e5ENh5uztgarug6VMKVa IEKKMDfDDTO8UfULyEPLHWQeRnQHBVMBPq8NFPRGq+JeRhykAGDLox6sCMXO+BMHoP sFgUAoEfG2zm6WrxHo8hYJFF4zEdDKxD3/6xhLEoUw06ZsXSpCkKd8Snq6ZXvqw/K1 BRzE7vr5n8D4A== From: Thomas Gleixner To: Ryan Chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-riscv@lists.infradead.org, Ryan Chen Subject: Re: [PATCH v2 1/5] dt-bindings: interrupt-controller: aspeed: Add AST2700-A2 support In-Reply-To: <20260306-irqchip-v2-1-f8512c09be63@aspeedtech.com> References: <20260306-irqchip-v2-0-f8512c09be63@aspeedtech.com> <20260306-irqchip-v2-1-f8512c09be63@aspeedtech.com> Date: Fri, 20 Mar 2026 09:24:55 +0100 Message-ID: <87tsualxgo.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri, Mar 06 2026 at 16:07, Ryan Chen wrote: > Introduce a new binding describing the AST2700 interrupt controller > architecture implemented in the A2 production silicon. > > The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2) > prior to mass production. The interrupt architecture was substantially > reworked after the A0 revision for A1, and the A1 design is retained > unchanged in the A2 production silicon. > > The existing AST2700 interrupt controller binding was written against > the pre-production A0 design. That binding does not accurately describe > the interrupt hierarchy and routing model present in A1/A2, where > interrupts can be routed to multiple processor-local interrupt > controllers (Primary Service Processor (PSP) GIC, Secondary Service > Processor (SSP)/Tertiary Service Processor (TSP) NVICs, and BootMCU > APLIC) depending on the execution context. > > Hardware connectivity between interrupt controllers is expressed using > the aspeed,interrupt-ranges property. Gentle reminder. Can the DT folks please have a look at this so we can make progress here? Thanks, tglx