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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042AD.mail.protection.outlook.com (10.167.243.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Fri, 21 Jun 2024 05:23:55 +0000 Received: from BLRRASHENOY1 (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 21 Jun 2024 00:23:51 -0500 From: Gautham R.Shenoy To: Perry Yuan , , , CC: , , , , Subject: Re: [PATCH v12 4/9] cpufreq: amd-pstate: initialize new core precision boost state In-Reply-To: References: Date: Fri, 21 Jun 2024 10:53:49 +0530 Message-ID: <87tthmvpga.fsf@BLR-5CG11610CF.amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AD:EE_|SJ2PR12MB8133:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cb7d46d-bd94-40f6-02b5-08dc91b258aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|1800799021|82310400023; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 05:23:55.5010 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cb7d46d-bd94-40f6-02b5-08dc91b258aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8133 Perry Yuan writes: > From: Perry Yuan > > Add one global `global_params` to represent CPU Performance Boost(cpb) > state for cpu frequency scaling, both active and passive modes all can > support CPU cores frequency boosting control which is based on the BIOS > setting, while BIOS turn on the "Core Performance Boost", it will > allow OS control each core highest perf limitation from OS side. > > The active, guided and passive modes of the amd-pstate driver can > support frequency boost control when the "Core Performance Boost" > (CPB) feature is enabled in the BIOS. When enabled in BIOS, the user > has an option at runtime to allow/disallow the cores from operating in > the boost frequency range. > > Add an amd_pstate_global_params object to record whether CPB is > enabled in BIOS, and if it has been activated by the user Can we rephrase this as : "The "Core Performance Boost (CPB) feature, when enabled in the BIOS, allows the OS to control the highest performance for each individual core. The active, passive and the guided modes of the amd-pstate driver do support controlling the core frequency boost when this BIOS feature is enabled. Additionally, the amd-pstate driver provides a sysfs interface allowing the user to activate/deactive this core performance boost featur at runtime. Add an amd_pstate_global_params object to record whether CPB is enabled in the BIOS, and if it has been activated by the user." > > Reported-by: Artem S. Tashkinov" > Cc: Oleksandr Natalenko > Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 > Signed-off-by: Perry Yuan > --- > drivers/cpufreq/amd-pstate.c | 59 +++++++++++++++++++++++++++++------- > drivers/cpufreq/amd-pstate.h | 13 ++++++++ > 2 files changed, 61 insertions(+), 11 deletions(-) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 5bdcdd3ea163..0c50b8ba16b6 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -102,6 +102,8 @@ static int cppc_state = AMD_PSTATE_UNDEFINED; > static bool cppc_enabled; > static bool amd_pstate_prefcore = true; > static struct quirk_entry *quirks; > +struct amd_pstate_global_params amd_pstate_global_params; > +EXPORT_SYMBOL_GPL(amd_pstate_global_params); > > /* > * AMD Energy Preference Performance (EPP) > @@ -694,7 +696,7 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) > > if (!cpudata->boost_supported) { > pr_err("Boost mode is not supported by this processor or SBIOS\n"); > - return -EINVAL; > + return -ENOTSUPP; > } > > if (state) > @@ -712,18 +714,38 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) > return 0; > } > > -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) > +static int amd_pstate_boost_set(struct amd_cpudata *cpudata) There is already an amd_pstate_set_boost(). The new name you are providing is amd_pstate_boost_set(). Makes it hard to read the code. Can we rename the existing amd_pstate_set_boost() to amd_pstate_update_boost() and keep amd_pstate_boost_set() for this function ? > { > - u32 highest_perf, nominal_perf; > + u64 boost_val; > + int ret = -1; > > - highest_perf = READ_ONCE(cpudata->highest_perf); > - nominal_perf = READ_ONCE(cpudata->nominal_perf); > + if (!cpu_feature_enabled(X86_FEATURE_CPB)) { > + pr_debug_once("Boost CPB capabilities not present in the processor\n"); > + ret = -EOPNOTSUPP; > + goto exit_err; > + } > > - if (highest_perf <= nominal_perf) > - return; > + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); > + if (ret) { > + pr_err_once("failed to read initial CPU boost state!\n"); > + ret = -EIO; > + goto exit_err; > + } > + > + amd_pstate_global_params.cpb_supported = !(boost_val & MSR_K7_HWCR_CPB_DIS); "amd_pstate_global_params.cpb_supported" will always contain the MSR_K7_HWCR[CPB_DIS] of the last CPU that calls amd_pstate_boost_set() since the code overwrites the value each time amd_pstate_boost_set() is called for cpudata. So would it be correct to assume the MSR_K7_HWCR[CPB_DIS] is going to be the same for every CPU ? -- Thanks and Regards gautham.