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Tue, 30 Jan 2024 11:59:55 +0000 Date: Tue, 30 Jan 2024 11:59:52 +0000 Message-ID: <87ttmvvxon.wl-maz@kernel.org> From: Marc Zyngier To: Lucas Stach Cc: Thomas Gleixner , Anup Patel , James Gowans , Koichiro Den , linux-kernel@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: Re: [PATCH] genirq: use relaxed access by default for irq_reg_{readl,writel} In-Reply-To: <20240129144502.1828154-1-l.stach@pengutronix.de> References: <20240129144502.1828154-1-l.stach@pengutronix.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 12.161.88.66 X-SA-Exim-Rcpt-To: l.stach@pengutronix.de, tglx@linutronix.de, apatel@ventanamicro.com, jgowans@amazon.com, den@valinux.co.jp, linux-kernel@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 29 Jan 2024 14:45:02 +0000, Lucas Stach wrote: > > irqchip access does not require any memory ordering between other > memory transactions and the IRQ controller peripheral access. > As all architectures now implement the relaxed MMIO accessors we > can switch the irq_reg_{readl,writel} helpers to use them, in > order to avoid potentially costly barriers in the IRQ handling > hotpath. > > Signed-off-by: Lucas Stach > --- > include/linux/irq.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/linux/irq.h b/include/linux/irq.h > index 90081afa10ce..fa1597db7887 100644 > --- a/include/linux/irq.h > +++ b/include/linux/irq.h > @@ -1218,7 +1218,7 @@ static inline void irq_reg_writel(struct irq_chip_generic *gc, > if (gc->reg_writel) > gc->reg_writel(val, gc->reg_base + reg_offset); > else > - writel(val, gc->reg_base + reg_offset); > + writel_relaxed(val, gc->reg_base + reg_offset); > } > > static inline u32 irq_reg_readl(struct irq_chip_generic *gc, > @@ -1227,7 +1227,7 @@ static inline u32 irq_reg_readl(struct irq_chip_generic *gc, > if (gc->reg_readl) > return gc->reg_readl(gc->reg_base + reg_offset); > else > - return readl(gc->reg_base + reg_offset); > + return readl_relaxed(gc->reg_base + reg_offset); > } > If this relaxation is introduced, it really should be documented and require a buy-in, because unsuspecting drivers may implicitly depend on the stronger ordering. I'm a strong advocate of the relaxed ordering, but changing this wholesale is potentially dangerous. M. -- Without deviation from the norm, progress is not possible.