From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56914EB64D8 for ; Tue, 20 Jun 2023 18:19:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229822AbjFTSTb (ORCPT ); Tue, 20 Jun 2023 14:19:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229675AbjFTST3 (ORCPT ); Tue, 20 Jun 2023 14:19:29 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCA351A8 for ; Tue, 20 Jun 2023 11:19:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687285168; x=1718821168; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=fxp7O1IFxzgSra3+U3m4CdtMmU0xIakqiwOKj7ZMuzc=; b=OKRX26P2xfDuDXHuogAZlOLCQshO1ptM5SxETE2boW46K7DgWFrCdkcU foQhNqw8ImGIez0fQI6CY88jv1D8rYrZBqb+1qCZ9+5UIYh2XsNlII5yp rEjCSC6h+PmgMC0U5qAOabhM0SvO2JlJzoZLjw1bLw9zQzh76UzggDPJa duYeranOu1vfID7rz1ie1f4XU34qDvuRroq/2yr89hXuqhtqNWIkhE18Y 1ekqmBbQtsM4b3+Tc7sCWgsC948JdOMLaA85SGg67CH1De8XNMYR6ON+y /9YyyQeGl+BCl9nyYntDsb7iF4rxj7gCAWeFwKrLnFUwpm+4QwzjA0dBF Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="363368698" X-IronPort-AV: E=Sophos;i="6.00,257,1681196400"; d="scan'208";a="363368698" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2023 11:19:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="838309700" X-IronPort-AV: E=Sophos;i="6.00,257,1681196400"; d="scan'208";a="838309700" Received: from dshvarts-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.62.204]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2023 11:19:23 -0700 From: Jani Nikula To: Andy Shevchenko , Lucas De Marchi Cc: Andrew Morton , intel-gfx@lists.freedesktop.org, Kevin Brodsky , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Christian =?utf-8?Q?K=C3=B6nig?= , Alex Deucher , Thomas Gleixner , Masahiro Yamada , intel-xe@lists.freedesktop.org Subject: Re: [Intel-xe] [PATCH 2/3] linux/bits.h: Add fixed-width GENMASK and BIT macros In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20230509051403.2748545-1-lucas.demarchi@intel.com> <20230509051403.2748545-3-lucas.demarchi@intel.com> <87pm75kd0h.fsf@intel.com> <87mt29kc34.fsf@intel.com> <875y7igph5.fsf@intel.com> Date: Tue, 20 Jun 2023 21:19:20 +0300 Message-ID: <87ttv2f13r.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 20 Jun 2023, Andy Shevchenko wrote: > So, what does prevent you from using GENMASK_ULL()? > > Another point, you may teach GENMASK() to issue a warning if hi and/or lo > bigger than BITS_PER_LONG. What good does that do if you want the warning for a fixed size different from unsigned long or long long? Worse, sizeof(long) depends on arch, while the GENMASK you want depends on the use case. > I still don't see the usefulness of that churn. This thread is turning into a prime example of why drivers and subsystems reinvent their own wheels instead of trying to get generally useful stuff merged in kernel headers. :p BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center