From: Marc Zyngier <maz@kernel.org>
To: wangwudi <wangwudi@hisilicon.com>
Cc: <linux-kernel@vger.kernel.org>, Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH] drivers: irqchip: Allocate alignment addr by ITS_BASER.Page_size
Date: Sat, 16 Jul 2022 10:30:19 +0100 [thread overview]
Message-ID: <87tu7h4d78.wl-maz@kernel.org> (raw)
In-Reply-To: <1657955136-6622-1-git-send-email-wangwudi@hisilicon.com>
On Sat, 16 Jul 2022 08:05:36 +0100,
wangwudi <wangwudi@hisilicon.com> wrote:
>
> The description of the ITS_BASER.Physical_Address field in the ARM GIC spec is as
> follows:
> "The address must be aligned to the size specified in the Page Size field."
> The Page_Size field in ITS_BASER might be RO.
>
> Currently, the address is aligned based on the system page_size, not the HW
> Page_Size field. In some case, this is in contradiction with the spec.
>
> For example:
> ITS_BASER.Page_Size indicate 16K, and kernel page size is 4K.
> If HW need 4K-size memory, the driver may alloc a 4K aligned address.
> This has been proven in hardware.
Ah, interesting bug. Thanks for bringing this up. Can you describe how
this occurs? I suspect you are using indirect tables.
>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Marc Zyngier <maz@kernel.org>
> Signed-off-by: wangwudi <wangwudi@hisilicon.com>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 5ff09de6c48f..0e25e887d45c 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -2310,6 +2310,9 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
> order = get_order(GITS_BASER_PAGES_MAX * psz);
> }
>
> + if ((psz > PAGE_SIZE) && (PAGE_ORDER_TO_SIZE(order) < psz)) {
> + order = get_order(psz);
> + }
> page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
> if (!page)
> return -ENOMEM;
However, I don't see how you end-up with the incorrect value here.
* No indirect table:
alloc_its_tables():
order = get_order(baser->psz);
* Indirect tables:
alloc_its_tables():
order = get_order(baser->psz);
its_parse_indirect_baser():
new_order = *order;
new_order = max_t(u32, get_order(esz << ids), new_order);
So in both cases, we should end-up with order >= get_order(psz).
Clearly, I'm missing a path, but your commit message doesn't make it
obvious. Can you please enlighten me?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-07-16 9:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-16 7:05 [PATCH] drivers: irqchip: Allocate alignment addr by ITS_BASER.Page_size wangwudi
2022-07-16 9:30 ` Marc Zyngier [this message]
2022-07-18 7:35 ` wangwudi
2022-07-19 8:33 ` Marc Zyngier
2022-07-21 8:46 ` wangwudi
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