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[193.12.47.89]) by smtp.gmail.com with ESMTPSA id c70sm59878lfd.87.2020.11.09.03.05.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2020 03:05:20 -0800 (PST) From: Tobias Waldekranz To: Vladimir Oltean Cc: Andrew Lunn , DENG Qingfang , Vivien Didelot , Florian Fainelli , Jakub Kicinski , netdev , linux-kernel@vger.kernel.org, Marek Behun , Russell King - ARM Linux admin Subject: Re: [RFC PATCH net-next 3/3] net: dsa: listen for SWITCHDEV_{FDB,DEL}_ADD_TO_DEVICE on foreign bridge neighbors In-Reply-To: <20201109100300.dgwce4nvddhgvzti@skbuf> References: <20201108131953.2462644-1-olteanv@gmail.com> <20201108131953.2462644-4-olteanv@gmail.com> <20201108172355.5nwsw3ek5qg6z7yx@skbuf> <20201108235939.GC1417181@lunn.ch> <20201109003028.melbgstk4pilxksl@skbuf> <87y2jbt0hq.fsf@waldekranz.com> <20201109100300.dgwce4nvddhgvzti@skbuf> Date: Mon, 09 Nov 2020 12:05:19 +0100 Message-ID: <87tutyu6xc.fsf@waldekranz.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 09, 2020 at 12:03, Vladimir Oltean wrote: > On Mon, Nov 09, 2020 at 09:09:37AM +0100, Tobias Waldekranz wrote: >> one. But now you have also increased the background load of an already >> choked resource, the MDIO bus. > > In practice, DSA switches are already very demanding of their management > interface throughput, for PTP and things like that. I do expect that if > you spent any significant amount of time with DSA, you already know the > ins and outs of your MDIO/SPI/I2C controller and it would already be > optimized for efficiency. But ok, we can add this to the list of cons. You are arguing for my position though, no? Yes it is demanding; that is why we must allocate it carefully. > So there you have it, it's not that bad. More work needs to be done, but > IMO it's still workable. If you bypass learning on all frames sent from the CPU (as today), yes I agree that you should be able to solve it with static entries. But I think that you will have lots of weird problems with initial packet loss as the FDB updates are not synchronous with the packet flow. I.e. the bridge will tell DSA to update the entry, but the update in HW will occur some time later when the workqueue actually performs the operation. > But now maybe it makes more sense to treat the switches that perform > hardware SA learning on the CPU port separately, after I've digested > this a bit. Yes, please. Because it will be impossible to add tx forward offloading otherwise.