From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C730F3A1A42 for ; Wed, 4 Feb 2026 10:53:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770202431; cv=none; b=dlbGytlKiLkiaxCebuRkt1H8iqMQSTRi8nHtpObXKZWQgo4TDAtAckD7I7WVBHApazA8E9c6OkmEz0s7E0fYT86CgjTXPT9hgbPuEvtvBwABxQHspsLGJ/iaxJoKgYJhZK+APOXbnRiS9fjn6aYo1/oWqjBHjhhTc5sXjz/VF9U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770202431; c=relaxed/simple; bh=BZ0oToVC1jitU9rObyP0MNLI/yQXQ7/ctuzujB2RK54=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=lOecsenAKmhIsdYK4Vp2B897rBiuwXJ1WRpav2nuxzErcQcrFpsoqTMCWierNf33DD223p+s9CojkusfKXXVuxgv5fMcMwTalgv6pnRfltLYIRlXoGKEyWijYJh9m7rsTDaGB72pEyUpqmd/AjcSBBrLWSB+AzaNGI2y+XZ9JBc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c/BPNA9v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c/BPNA9v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C18ACC4CEF7; Wed, 4 Feb 2026 10:53:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770202431; bh=BZ0oToVC1jitU9rObyP0MNLI/yQXQ7/ctuzujB2RK54=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=c/BPNA9vn8g3Di9lBqxmKqzMT5UO0OCzRlPGxvsFW+Gjc1obqYkq3Qo7MRq/bytOg a5IGeNz8nKnkZyjjcv7kUReZuPf/0VlvBzxFS52shcFelIaTNUcfeYM7mUQBHVtxtr 68M7v0Onp3czp9bz0PBRjChLtEONz3g+hB6S2zd/nrQDWML0DDz00qlbIV6sWfx8TK rkMporN0FdBxd30MU4e0y3gQ1Vv0tJjVPLCuxtrs0h7NlDkGTVK9DP9HYvbThS0Ecw qzHBORYl6AEtBMax7jldGCQznIIpsn55LgmeakNm7HIbmH/o0ZR7BhJ6ocVfooZUeS kjP8yZgPI7dNQ== From: Thomas Gleixner To: Peter Zijlstra , Mathieu Desnoyers Cc: LKML , Ihor Solodrai , Shrikanth Hegde , Michael Jeanson Subject: Re: [patch V2 0/4] sched/mmcid: Cure mode transition woes In-Reply-To: <20260202125430.GD1395266@noisy.programming.kicks-ass.net> References: <20260201192234.380608594@kernel.org> <20260202101424.GB3016024@noisy.programming.kicks-ass.net> <2adfed8a-c844-423e-8638-519db7f8a0cb@efficios.com> <20260202125430.GD1395266@noisy.programming.kicks-ass.net> Date: Wed, 04 Feb 2026 11:53:48 +0100 Message-ID: <87v7gc230j.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Mon, Feb 02 2026 at 13:54, Peter Zijlstra wrote: > On Mon, Feb 02, 2026 at 06:46:34AM -0500, Mathieu Desnoyers wrote: >> On 2026-02-02 05:14, Peter Zijlstra wrote: >> > On Mon, Feb 02, 2026 at 10:39:35AM +0100, Thomas Gleixner wrote: >> > >> > > --- a/kernel/sched/core.c >> > > +++ b/kernel/sched/core.c >> > > @@ -10445,6 +10445,12 @@ static bool mm_update_max_cids(struct mm >> > > /* Flip the mode and set the transition flag to bridge the transfer */ >> > > WRITE_ONCE(mc->mode, mc->mode ^ (MM_CID_TRANSIT | MM_CID_ONCPU)); >> > > + /* >> > > + * Order the store against the subsequent fixups so that >> > > + * acquire(rq::lock) cannot be reordered by the CPU before the >> > > + * store. >> > > + */ >> > > + smp_mb(); >> > > return true; >> > > } >> > > @@ -10487,6 +10493,16 @@ static inline void mm_update_cpus_allowe >> > > irq_work_queue(&mc->irq_work); >> > > } >> > > +static inline void mm_cid_complete_transit(struct mm_struct *mm, unsigned int mode) >> > > +{ >> > > + /* >> > > + * Ensure that the store removing the TRANSIT bit cannot be >> > > + * reordered by the CPU before the fixups have been completed. >> > > + */ >> > > + smp_mb(); >> > > + WRITE_ONCE(mm->mm_cid.mode, mode); >> > > +} >> > >> > I think this could've been smp_store_release(), but this is the slow >> > path so nobody cares and this is nicely symmetric. >> >> I'm not sure the store-release would work here. What load-acquire >> would it pair with ? > > The purpose here -- per the comment is to ensure the fixup stuff is > visible before the TRANSIT bit goes 0, store-release ensures that. > > That pairs with whatever cares about this barrier now. I thought about this and stopped reading memory-barriers.txt after brain started to hurt. acquire A store B release A acquire C store D release C A and C are independent of each other as are B and D. So according to the docs acquire C can be reordered before release A. So far so good. But what's unclear to me is whether this scenarion is possible: acquire A acquire C store D release C store B release A because that would screw up stuff badly. Thanks, tglx