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From: Thomas Gleixner <tglx@kernel.org>
To: Icenowy Zheng <zhengxingda@iscas.ac.cn>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Huacai Chen <chenhuacai@kernel.org>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-mips@vger.kernel.org,
	Icenowy Zheng <zhengxingda@iscas.ac.cn>
Subject: Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code
Date: Sun, 01 Feb 2026 17:19:45 +0100	[thread overview]
Message-ID: <87v7ggfnby.ffs@tglx> (raw)
In-Reply-To: <20260131094547.455916-6-zhengxingda@iscas.ac.cn>

On Sat, Jan 31 2026 at 17:45, Icenowy Zheng wrote:

> As the (kernel-internally) OF-based MIPS Loongson-3 systems can also

What are kernel-internally systems?

> have PCH LPC interrupt controller, add OF-based initialization code for

have a ... controller.

Add OF ....

> +#ifdef CONFIG_OF
> +static int pch_lpc_of_init(struct device_node *node,
> +				struct device_node *parent)

No line break required.

> +{
> +	int parent_irq;
> +	struct fwnode_handle *irq_handle;
> +	struct resource res;

Variable ordering.

> +	if (of_address_to_resource(node, 0, &res))
> +		return -EINVAL;
> +
> +	parent_irq = irq_of_parse_and_map(node, 0);
> +	if (!parent_irq) {
> +		pr_err("Failed to get the parent IRQ for LPC IRQs\n");
> +		return -EINVAL;
> +	}
> +
> +	irq_handle = of_fwnode_handle(node);
> +
> +	return pch_lpc_init(res.start, resource_size(&res), irq_handle,
> +			    parent_irq);

If pch_lpc_init() fails the parent interrupt mapping is leaked, no?

Thanks,

        tglx

  parent reply	other threads:[~2026-02-01 16:19 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-31  9:45 [PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems Icenowy Zheng
2026-01-31  9:45 ` [PATCH 1/8] genirq: reserve NR_IRQS_LEGACY IRQs in dynirq by default Icenowy Zheng
2026-01-31  9:45 ` [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC Icenowy Zheng
2026-02-09 23:48   ` Rob Herring
2026-02-10  6:33     ` Icenowy Zheng
2026-02-10 10:51     ` Icenowy Zheng
2026-02-10 12:47       ` Huacai Chen
2026-01-31  9:45 ` [PATCH 3/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init Icenowy Zheng
2026-01-31 14:05   ` kernel test robot
2026-02-01 16:15   ` Thomas Gleixner
2026-01-31  9:45 ` [PATCH 4/8] irqchip/loongson-pch-lpc: guard ACPI init code with CONFIG_ACPI Icenowy Zheng
2026-01-31  9:45 ` [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code Icenowy Zheng
2026-01-31 19:59   ` kernel test robot
2026-02-01  2:33   ` Huacai Chen
2026-02-01 16:17     ` Thomas Gleixner
2026-02-01 16:19   ` Thomas Gleixner [this message]
2026-02-02  5:50     ` Icenowy Zheng
2026-02-02  9:55       ` Thomas Gleixner
2026-02-02  1:12   ` kernel test robot
2026-01-31  9:45 ` [PATCH 6/8] irqchip/loongson-pch-lpc: enable building on MIPS Loongson64 Icenowy Zheng
2026-01-31  9:45 ` [PATCH 7/8] MIPS: Loongson64: dts: sort nodes Icenowy Zheng
2026-01-31  9:45 ` [PATCH 8/8] MIPS: Loongson64: dts: add node for LS7A PCH LPC Icenowy Zheng
2026-02-01  9:57 ` [PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems Yao Zi

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