Re: RFC: Memory Tiering Kernel Interfaces

Wei Xu
2022-05-04T01:31:46Z

On Tue, May 3, 2022 at 4:54 PM Dave Hansen <dave.hansen@intel.com> wrote:
>
> On 5/3/22 15:35, Alistair Popple wrote:
> > Not entirely true. The GPUs on POWER9 have performance counters capable of
> > collecting this kind of information for memory accessed from the GPU. I will
> > admit though that sadly most people probably don't have a P9 sitting under their
> > desk :)
>
> Well, x86 CPUs have performance monitoring hardware that can
> theoretically collect physical access information too. But, this
> performance monitoring hardware wasn't designed for this specific use
> case in mind. So, in practice, these events (PEBS) weren't very useful
> for driving memory tiering.

The PEBS events without any filtering might not be useful for memory
tiering, but the PEBS events with hardware-based data source filtering
can be useful in driving promotions in memory tiering. Certainly,
because these events are not designed for this specific use case in
mind, there are inefficiencies using them for memory tiering, e.g.
instead of just getting a heat counter for each hot page, we can get
events repeatedly on the hot pages.

> Are you saying that the GPUs on POWER9 have performance counters that
> can drive memory tiering in practice? I'd be curious if there's working
> code to show how they get used. Maybe the hardware is better than the
> x86 PMU or the software consuming it is more clever than what we did.
> But, I'd love to see it either way.