From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750941AbdAQH7s (ORCPT ); Tue, 17 Jan 2017 02:59:48 -0500 Received: from smtp06.smtpout.orange.fr ([80.12.242.128]:56397 "EHLO smtp.smtpout.orange.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750787AbdAQH7q (ORCPT ); Tue, 17 Jan 2017 02:59:46 -0500 X-ME-Helo: belgarion X-ME-Auth: amFyem1pay5yb2JlcnRAb3JhbmdlLmZy X-ME-Date: Tue, 17 Jan 2017 08:59:00 +0100 X-ME-IP: 92.149.56.251 From: Robert Jarzmik To: Jan Kiszka Cc: Mark Brown , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Mack , Haojian Zhuang , linux-kernel@vger.kernel.org, Andy Shevchenko , Mika Westerberg , Jarkko Nikula , Sascha Weisenberger Subject: Re: [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts References: <7b15a0910a3ad861fd32161c72559bafa7b71e29.1484592296.git.jan.kiszka@siemens.com> X-URL: http://belgarath.falguerolles.org/ Date: Tue, 17 Jan 2017 08:58:58 +0100 In-Reply-To: <7b15a0910a3ad861fd32161c72559bafa7b71e29.1484592296.git.jan.kiszka@siemens.com> (Jan Kiszka's message of "Mon, 16 Jan 2017 19:44:55 +0100") Message-ID: <87vatedsn1.fsf@belgarion.home> User-Agent: Gnus/5.130008 (Ma Gnus v0.8) Emacs/24.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Jan Kiszka writes: > When using the a device with edge-triggered interrupts, such as MSIs, > the interrupt handler has to ensure that there is a point in time during > its execution where all interrupts sources are silent so that a new > event can trigger a new interrupt again. > > This is achieved here by looping over SSSR evaluation. We need to take > into account that SSCR1 may be changed by the transfer handler, thus we > need to redo the mask calculation, at least regarding the volatile > interrupt enable bit (TIE). I'd like moreover to add a question here. In pxa architecture, SPI interrupts are already edge-triggered, and it's working well. The interrupt source disabling is not disabled, but the interrupt controller doesn't trigger an interrupt anymore (as it is masked), yet it marks it as pending if an interrupt arrives while the interrupt handler is running. All of this is handled by the interrupt core. My question is why for Intel MSI's is it necessary to make a change in the driver instead or relying on the interrupt core as for the pxa ? Cheers. -- Robert