From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F0783DB628 for ; Wed, 3 Jun 2026 15:57:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780502245; cv=none; b=Xk8L0i7d/WxerDXCzyBTAj8oGdOfsqeBeK7j3qrnHSuf4uBlTWz0YN72Ng5p5UMYlUIli+oM6UGmepeQMyIohcNVrZnhc8Qn4IlhpBm5OAvprN3RHWrTWue6CRzBWsUC/b7qKpjoie5Y2qx5c0jEDh5beuhkl5pOWaSB4dhsuQk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780502245; c=relaxed/simple; bh=y8fnEaREQlnSPCiUDO1AiGaGfQ0oK03TQ2JibT6+sjU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=TSAbkkav5OTdA2wPJG77UM2F185W7KJCCw2ueItGp/O5zzRz9KlNgPB1DJ89katcutstHgGRR+aNpMMFbAn+tkGSgQtUx7DP5N/+pjmwwqVNI54enYvKnPpXazVajM+prcuRibUdzBgRn+62x2eiPPjx911iiO/sMMc4kcjbG50= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=epW1Ew1b; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="epW1Ew1b" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 334381F00898; Wed, 3 Jun 2026 15:57:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780502244; bh=/Q4H2B6JPCTrhv1HVXSIXl9RrHqVkzup65JEmQTVAxM=; h=From:To:Cc:Subject:In-Reply-To:References:Date; b=epW1Ew1bUzDOcnjlhiIt5ro2NJQMpz33M2Fs6WUya27SlCBddfSzsL98YbzzVbCNe OIxt/FUFbcBEcg0Gl29xUKILPn+hni7jaA22lh9PcaTJRVDnTUVfW+HjHV1GkNkJjd a41+zMlP9Voj4SFxkk89WPOZD7zP9dgELW37abpMj94pOTYP9lInSe+PXyK3xmh/ZP eX3pi4XkOLvSVZXzfA8OLaEeGT5xdVal5IH+Kw2EBcqtjiKq6DBLetK6ddXklQR3cO +3nkr3OKVj7Wx2DBgOVsWL42EhVZghl7H9+OwcB3yg9dDlK+6GSwTaoRNZeul8v7kU vKG2CGOC/zQlg== From: Thomas Gleixner To: Markus Stockhausen , linux-kernel@vger.kernel.org Cc: Markus Stockhausen Subject: Re: [PATCH 1/2] irqchip/irq-realtek-rtl: Add/simplify register helpers In-Reply-To: <20260512184646.1896480-2-markus.stockhausen@gmx.de> References: <20260512184646.1896480-1-markus.stockhausen@gmx.de> <20260512184646.1896480-2-markus.stockhausen@gmx.de> Date: Wed, 03 Jun 2026 17:57:20 +0200 Message-ID: <87wlwf62hr.ffs@fw13> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, May 12 2026 at 20:46, Markus Stockhausen wrote: > The Realtek IRQ controller has two important registers that s/IRQ/interrupt/ This is not a SMS service. > > -static void write_irr(void __iomem *irr0, int idx, u32 value) > +static inline void enable_gimr(int hw_irq) unsigned int hw_irq > { > - unsigned int offset = IRR_OFFSET(idx); > - unsigned int shift = IRR_SHIFT(idx); > + u32 gimr; > + > + gimr = readl(REG(RTL_ICTL_GIMR)); > + gimr |= BIT(hw_irq); > + writel(gimr, REG(RTL_ICTL_GIMR)); > +} > + > +static inline void disable_gimr(int hwirq) Ditto > +{ > + u32 gimr; > + > + gimr = readl(REG(RTL_ICTL_GIMR)); > + gimr &= ~BIT(hwirq); > + writel(gimr, REG(RTL_ICTL_GIMR)); > +} > + > +static void write_irr(int hw_irq, u32 value) > +{ > + void __iomem *irr0 = REG(RTL_ICTL_IRR0); > + unsigned int offset = IRR_OFFSET(hw_irq); > + unsigned int shift = IRR_SHIFT(hw_irq); > u32 irr; > > irr = readl(irr0 + offset) & ~(0xf << shift); > @@ -51,28 +70,18 @@ static void write_irr(void __iomem *irr0, int idx, u32 value) > static void realtek_ictl_unmask_irq(struct irq_data *i) > { > unsigned long flags; > - u32 value; > > raw_spin_lock_irqsave(&irq_lock, flags); Please convert that to guard(raw_spinlock)(&lock); while at it. No _irqsave required as mask/unmask are invoked with the interrupt descriptor lock held and interrupts disabled. > static void realtek_ictl_mask_irq(struct irq_data *i) > { > unsigned long flags; > - u32 value; > > raw_spin_lock_irqsave(&irq_lock, flags); Ditto > - > - value = readl(REG(RTL_ICTL_GIMR)); > - value &= ~BIT(i->hwirq); > - writel(value, REG(RTL_ICTL_GIMR)); > - > + disable_gimr(i->hwirq); > raw_spin_unlock_irqrestore(&irq_lock, flags); > } > > @@ -89,7 +98,7 @@ static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) > irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); > guard(raw_spinlock_irq)(&lock); _irq because this is task context. > raw_spin_lock_irqsave(&irq_lock, flags); > - write_irr(REG(RTL_ICTL_IRR0), hw, 1); > + write_irr(hw, 1); > raw_spin_unlock_irqrestore(&irq_lock, flags); > > return 0; > @@ -135,9 +144,10 @@ static int __init realtek_rtl_of_init(struct device_node *node, struct device_no > return -ENXIO; > > /* Disable all cascaded interrupts and clear routing */ > - writel(0, REG(RTL_ICTL_GIMR)); > - for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) > - write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0); > + for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) { Please make that for (unsigned int soc_irq = 0; .... and remove the declaration at the top of the function. Thanks, tglx