From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C482DF58 for ; Sun, 8 Sep 2024 09:38:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725788281; cv=none; b=OEnzvGqv1gB5FIF3Lp89qiYlTf1J1m5yjbgJ0rxMGGLdBJqnZ8W8CZ7PHFjZ2FDJYQJ3AbX2cwquJXky5QLfquuRNDDx5aobHDPVO77hnuRPQvhEFZY6HMIqV8IHxyXZwRe18B2P9XYTREinKzBUOKRI+K/4KfwlyOmc+3LT2to= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725788281; c=relaxed/simple; bh=siJn425AxZ5+7HkM3BgAENCGYl7MdXTqBPGST4nKFcY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=elHSXK2FjKYaTVB5+DT5jwJe46wn6lwUPi7M8uDd6BL9Ee583eS/MM23joP/kyzaCPSKWFnb6G/41OSb2BIQgLDlSdFBA3T2QoOcOpEIWCcHERzrROKDDw0bRvC1xB/PkCD4JygVXb3HHBMaI041RRwV2lnIX6Q0ZjIfwZxffcg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lPLeRvTG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lPLeRvTG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D9B76C4CEC3; Sun, 8 Sep 2024 09:38:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725788280; bh=siJn425AxZ5+7HkM3BgAENCGYl7MdXTqBPGST4nKFcY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lPLeRvTGFAWE1X2IoSaZ9WkgMsVRhhTxDBU+ZjXIiQEw6hgN9Cwly5XSQSoUTMoTA Sl9HGCWYZaamEKPCuzJ+4h8zFZvh/oqS2FuugJeA/C3nCb2WSYjU5nGOtH/w6Btebd 4yJZuewcfwF2kOiXfA9e4tIC0ATJ5PqCCdwQG+ygYG11hWir1DQEV30AwaXD5SE45z R/CW5V364aAXx1Nvc37ea1OUrgFVEAWAABu0WOoLsSZC5BBGoMr4aUwM40AHX73mEI YWd8Kw5eebZWZKQpRXY/Z1xxKvYOUh+BZDvFCsTSE+ccG1XgLT/3v60fVsv/Hsh2sC uL24p8s/3JWtA== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1snEMo-00Aczu-ST; Sun, 08 Sep 2024 10:37:59 +0100 Date: Sun, 08 Sep 2024 10:37:53 +0100 Message-ID: <87wmjmv632.wl-maz@kernel.org> From: Marc Zyngier To: Sergey Shtylyov Cc: Thomas Gleixner , , Subject: Re: [PATCH] irqchip/gic: prevent buffer overflow in gic_ipi_send_mask() In-Reply-To: References: <048ff3bb-09d1-2e60-4f3b-611e2bfde7aa@omp.ru> <87cyli5zj7.ffs@tglx> <86o752v8xs.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: s.shtylyov@omp.ru, tglx@linutronix.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 06 Sep 2024 21:29:47 +0100, Sergey Shtylyov wrote: > > On 9/5/24 10:47 AM, Marc Zyngier wrote: > [...] > > >>> ARM GIC arch v2 spec claims support for just 8 CPU interfaces. However, > >>> looking at the GIC driver's irq_set_affinity() method, it seems that the > >>> passed CPU mask may contain the logical CPU #s beyond 8, and that method > >>> filters them out before reading gic_cpu_map[], bailing out with > >>> -EINVAL. > >> > >> The reasoning is correct in theory, but in reality it's a non problem. > >> > >> Simply because processors which use this GIC version cannot have more > >> than 8 cores. > >> > >> That means num_possible_cpus() <= 8 so the cpumask handed in cannot have > >> bits >= 8 set. Ergo for_each_cpu() can't return a bit which is >= 8. > > > > That. > > That? :-) What Thomas explained. > > > The irq_set_affinity() check exists because the affinity can be > > provided by userspace, and used to be be *anything*. Since > > In this case you mean gic_set_affinity(), right? Yes. > > > 33de0aa4bae98, the affinity that the driver gets is narrowed to what > > is actually *online*. > > What I haven't quite understood from my (cursory) looking at the GICv2 > spec (and the GIC driver) is why only one CPU (with a lowest #) is selected > from *mask_val before writing to GICD_GIC_DIST_TARGET, while the spec holds > that an IRQ can be forwarded to any set of 8 CPU interfaces... Because on all the existing implementations, having more than a single target in GICD_ITARGETSRn results in all the targeted CPUs to be interrupted, with the guarantee that only one will see the actual interrupt (the read from GICC_IAR returns a value that is not 0x3ff), and everyone else will only see a spurious interrupt (0x3ff). This is because the distributor does not track which CPU is actually in a position to handle the interrupt. While this can be, under limited circumstances, beneficial from an interrupt servicing latency, it is always bad from a global throughput perspective. You end-up thrashing CPU caches, generating odd latencies in unsuspecting code, and in general with disappointing performance. Thankfully, GIC (v1/v2) is a dead horse, and v3 doesn't have this particular problem (it replaced it with a bigger one in the form of 1:n distribution). M. -- Without deviation from the norm, progress is not possible.