From: Marc Zyngier <maz@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Biju Das <biju.das.au@gmail.com>,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 2/3] irqchip: renesas-rzg2l: Mask interrupts for changing interrupt settings
Date: Sun, 24 Sep 2023 10:27:13 +0100 [thread overview]
Message-ID: <87wmwf53bi.wl-maz@kernel.org> (raw)
In-Reply-To: <20230918122411.237635-3-biju.das.jz@bp.renesas.com>
On Mon, 18 Sep 2023 13:24:10 +0100,
Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> As per RZ/G2L hardware manual Rev.1.30 section 8.8.3 Precaution when
> changing interrupt settings, we need to mask the interrupts for
> any changes in below settings:
>
> * When changing the noise filter settings.
> * When switching the GPIO pins to IRQ or GPIOINT.
> * When changing the source of TINT.
> * When changing the interrupt detection method.
>
> This patch masks the interrupts when there is a change in the interrupt
> detection method and changing the source of TINT.
>
> Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
> index 2cee5477be6b..33a22bafedcd 100644
> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -116,11 +116,13 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d)
> u8 tssr_index = TSSR_INDEX(offset);
> u32 reg;
>
> + irq_chip_mask_parent(d);
> raw_spin_lock(&priv->lock);
> reg = readl_relaxed(priv->base + TSSR(tssr_index));
> reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
> writel_relaxed(reg, priv->base + TSSR(tssr_index));
> raw_spin_unlock(&priv->lock);
> + irq_chip_unmask_parent(d);
What guarantees that the parent irqchip state has been correctly restored?
Nothing refcounts the nesting of mask/unmask.
> }
> irq_chip_disable_parent(d);
I'd rather you start by *disabling* the parent, and then none of that
matters at all.
> }
> @@ -137,11 +139,13 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d)
> u8 tssr_index = TSSR_INDEX(offset);
> u32 reg;
>
> + irq_chip_mask_parent(d);
> raw_spin_lock(&priv->lock);
> reg = readl_relaxed(priv->base + TSSR(tssr_index));
> reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset);
> writel_relaxed(reg, priv->base + TSSR(tssr_index));
> raw_spin_unlock(&priv->lock);
> + irq_chip_unmask_parent(d);
> }
> irq_chip_enable_parent(d);
Same thing: if the parent was disabled, why do we need to do anything?
> }
> @@ -226,10 +230,12 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
> unsigned int hw_irq = irqd_to_hwirq(d);
> int ret = -EINVAL;
>
> + irq_chip_mask_parent(d);
> if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
> ret = rzg2l_irq_set_type(d, type);
> else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
> ret = rzg2l_tint_set_edge(d, type);
> + irq_chip_unmask_parent(d);
This one is the only interesting one: why don't you mask the interrupt
at the local level rather than on the parent? And this should be
conditioned on the interrupt state itself (enabled or disabled), not
done unconditionally.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2023-09-24 9:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-18 12:24 [PATCH 0/3] Fix IRQ storm with GPIO interrupts Biju Das
2023-09-18 12:24 ` [PATCH 1/3] irqchip: renesas-rzg2l: Fix logic to clear TINT interrupt source Biju Das
2023-09-18 12:38 ` Geert Uytterhoeven
2023-09-19 5:56 ` claudiu beznea
2023-09-24 9:31 ` [irqchip: irq/irqchip-fixes] " irqchip-bot for Biju Das
2023-09-18 12:24 ` [PATCH 2/3] irqchip: renesas-rzg2l: Mask interrupts for changing interrupt settings Biju Das
2023-09-24 9:27 ` Marc Zyngier [this message]
2023-09-25 8:51 ` Biju Das
2023-09-18 12:24 ` [PATCH 3/3] irqchip: renesas-rzg2l: Fix irq storm with edge trigger detection for TINT Biju Das
2023-09-19 14:37 ` Marc Zyngier
2023-09-19 15:24 ` Biju Das
2023-09-19 16:19 ` Marc Zyngier
2023-09-19 16:32 ` Biju Das
2023-09-19 16:49 ` Marc Zyngier
2023-09-19 17:06 ` Biju Das
2023-09-21 7:55 ` Marc Zyngier
2023-09-22 14:34 ` Biju Das
2023-10-06 10:46 ` Biju Das
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87wmwf53bi.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=biju.das.au@gmail.com \
--cc=biju.das.jz@bp.renesas.com \
--cc=claudiu.beznea.uj@bp.renesas.com \
--cc=geert+renesas@glider.be \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox