From: Marc Zyngier <maz@kernel.org>
To: Jianmin Lv <lvjianmin@loongson.cn>
Cc: Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org, loongarch@lists.linux.dev,
Hanjun Guo <guohanjun@huawei.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@loongson.cn>
Subject: Re: [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers
Date: Sun, 17 Jul 2022 15:49:11 +0100 [thread overview]
Message-ID: <87wncbzteg.wl-maz@kernel.org> (raw)
In-Reply-To: <20994a99-b5b1-442d-d23d-2a11ecef24a0@loongson.cn>
On Sun, 17 Jul 2022 12:29:05 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
>
>
> On 2022/7/17 下午6:02, Marc Zyngier wrote:
> > But the other issue is that you seem to call this function from two
> > different locations. This cannot be right, as there should be only one
> > probe order, and not multiple.
> >
>
> As we described two IRQ models(Legacy and Extended) in this cover
> letter, the parent domain of MSI domain can be htvec domain(Legacy) or
> eiointc domain(Extended). In MADT, only one APIC(HTPIC for htvec or
> EIOPIC for eiointc) is allowed to pass into kernel, and then in the
> irqchip driver, only one kind APIC of them can be parsed from MADT, so
> we have to support two probe order for them.
Do you really have the two variants in the wild? Or is this just
because this is a possibility?
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2022-07-17 14:49 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 7:05 [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 01/15] ACPICA: MADT: Add LoongArch APICs support Jianmin Lv
2022-07-16 18:10 ` Marc Zyngier
2022-07-17 1:05 ` Jianmin Lv
2022-07-18 12:28 ` Jianmin Lv
2022-07-18 13:26 ` Marc Zyngier
2022-07-15 7:05 ` [PATCH V15 02/15] APCI: irq: Add support for multiple GSI domains Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 04/15] genirq/generic_chip: export irq_unmap_generic_chip Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 05/15] LoongArch: Use ACPI_GENERIC_GSI for gsi handling Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 06/15] irqchip: Add Loongson PCH LPC controller support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 07/15] irqchip: remove COMPILE_TEST for pch-pic and pch-msi Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 08/15] irqchip/loongson-pch-pic: Add ACPI init support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 09/15] irqchip/loongson-pch-msi: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 10/15] irqchip/loongson-htvec: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 11/15] irqchip/loongson-liointc: " Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 12/15] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 13/15] irqchip: Add Loongson Extended I/O interrupt controller support Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 14/15] irqchip: Add LoongArch CPU " Jianmin Lv
2022-07-15 15:11 ` Huacai Chen
2022-07-17 12:02 ` Jianmin Lv
2022-07-15 7:05 ` [PATCH V15 15/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch Jianmin Lv
2022-07-16 18:39 ` [PATCH V15 00/15] irqchip: Add LoongArch-related irqchip drivers Marc Zyngier
2022-07-17 1:06 ` Jianmin Lv
2022-07-17 10:02 ` Marc Zyngier
2022-07-17 11:29 ` Jianmin Lv
2022-07-17 14:08 ` Huacai Chen
2022-07-17 14:43 ` Marc Zyngier
2022-07-18 2:38 ` Huacai Chen
2022-07-18 6:43 ` Marc Zyngier
2022-07-18 8:35 ` Huacai Chen
2022-07-17 14:49 ` Marc Zyngier [this message]
2022-07-18 1:07 ` Jianmin Lv
2022-07-18 6:39 ` Marc Zyngier
2022-07-18 8:29 ` Jianmin Lv
2022-07-18 8:39 ` Huacai Chen
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