From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030833AbbEETxS (ORCPT ); Tue, 5 May 2015 15:53:18 -0400 Received: from gabe.freedesktop.org ([131.252.210.177]:43301 "EHLO gabe.freedesktop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932083AbbEETxP (ORCPT ); Tue, 5 May 2015 15:53:15 -0400 From: Eric Anholt To: Stephen Warren Cc: linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lee Jones , popcornmix@gmail.com Subject: Re: [PATCH] ARM: bcm2835: Use 0x4 prefix for DMA bus addresses to SDRAM. In-Reply-To: <55491A12.3070608@wwwdotorg.org> References: <1430768034-12734-1-git-send-email-eric@anholt.net> <55491A12.3070608@wwwdotorg.org> User-Agent: Notmuch/0.18.2 (http://notmuchmail.org) Emacs/24.4.1 (x86_64-pc-linux-gnu) Date: Tue, 05 May 2015 12:53:09 -0700 Message-ID: <87wq0mol7e.fsf@eliezer.anholt.net> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha512; protocol="application/pgp-signature" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Stephen Warren writes: > On 05/04/2015 01:33 PM, Eric Anholt wrote: >> There exists a tiny MMU, configurable only by the VC (running the >> closed firmware), which maps from the ARM's physical addresses to bus >> addresses. These bus addresses determine the caching behavior in the >> VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top >> 2 bits. The bits in the bus address mean: >> >> From the VideoCore processor: >> 0x0... L1 and L2 cache allocating and coherent >> 0x4... L1 non-allocating, but coherent. L2 allocating and coherent >> 0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent >> 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or cohere= nt >> >> From the GPU peripherals (note: all peripherals bypass the L1 >> cache. The ARM will see this view once through the VC MMU): >> 0x0... Do not use >> 0x4... L1 non-allocating, and incoherent. L2 allocating and coherent. >> 0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent >> 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or cohere= nt >> >> The 2835 firmware always configures the MMU to turn ARM physical >> addresses with 0x0 top bits to 0x4, meaning present in L2 but >> incoherent with L1. However, any bus addresses we were generating in >> the kernel to be passed to a device had 0x0 bits. That would be a >> reserved (possibly totally incoherent) value if sent to a GPU >> peripheral like USB, or L1 allocating if sent to the VC (like a >> firmware property request). By setting dma-ranges, all of the devices >> below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and >> friends return addresses with 0x4 bits and avoid cache incoherency. >> >> This matches the behavior in the downstream 2708 kernel (see >> BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h). > >> diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.= dtsi > >> #address-cells =3D <1>; >> #size-cells =3D <1>; >> ranges =3D <0x7e000000 0x20000000 0x02000000>; >> + dma-ranges =3D <0x40000000 0x00000000 0x1f000000>; > > Oh well that's a nice and simple patch; I had been avoiding looking into= =20 > fixing the kernel for this since I was worried it'd be rather complex! > > I'm puzzled why the length cell of ranges and dma-ranges differs though?= =20 > Assuming there's a good explanation for that, Nope, you're right, it should be 0x20000000. '0x1f' came from going back from the '0x3f' on the pi2, but pi2 just has a chunk lost to the bus mapping. --=-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBCgAGBQJVSR+lAAoJELXWKTbR/J7ovxQP/i0V3oRW8KDBKQ6mi57NfIpB 5NLpqSSY0TR7Cl0LCH8u2/V5n6YEsTgr+pGJbp84sJwZGFunHp7ELfxcOzSBmLi5 fglEWPm2+1HFKzHVvvROZ0h/uon2r/JtFg5Prp5e9y9JshFiSoFhpulZZ6hjhYQA WiAWJ5hONCN5hNKbZQDbsbDlj6ayq91ewu0QyJF65A3C4m03I/q6bD60sE6XW6jh siD+1BKszQN3AQBW5BetPr7guGHXqaoqqf1+pVup5NCRLfE7iyYZCYghpSiBHmdd q+l7tDbuvW6+O2S4X5JkJHYsAWcoOmOuNGP/vQfZ69rZ3mE3tMvXdn0Hcd7RHK8n znSoOS+tsdOd0Fh4pXJP88Dmc88SlyWIvN4jw9+AY/gCfmMzo1SFzJxhdGpSgGou 1pkSubXQTgZk2HkGwB3UWpj8nmso2e1nmkBMUn8UVyAeG3A5uQg6aqwtyU+6bHXF 89qQUwTufKfA7JX9TfSBOgWuv2kNEEQCs1MrqiwDu/74iAxHxoDGjJkqZ4q5NCge wMpWHKwwSCC/w/EiGO22nQ+nbegGj5uCMqE1w3xFxYpOsTq0FOWlk/tRl8cvqasN tdZCW7nR/Vz4az4srV3PByLKeDj9+k5swi8HbE6gckEez1Fh2xOCCIhLQOUqfHnd x+SXe3kcbr1KEt7j5WDx =bgTl -----END PGP SIGNATURE----- --=-=-=--