From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 363EF3242D9 for ; Wed, 5 Aug 2026 14:05:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785938717; cv=none; b=VO6U77nZBjsPgpVW1L/zMMWmS3bbH5I/uYVgXP8mUj8pxbM4smXs0XaZ8Xm7s7eOoOdWsoquFIr2f6OAsj8EgbW8sJGB+NckbCRXPyVX/b85ejI2Lq7nJuT64FHHi8dkW5PrQuNxs5ufS6d91nA6Q2+jCo+G8gwqR+h64X+ptR4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785938717; c=relaxed/simple; bh=x3JStsuMw4xJlF6thwDamLu+cxEYkY3eCDtwR/ZEY/g=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=QSxmSc3o9B5bm0v/rmy2G1gU/JHFAp1jXuNcVHuPgPoZmcPYT1IHOjjXLbTlJQsFxd1EmxP/3o0Z02/tm+nRP1xala8YAL4uY7FP9ETqf1QF+GbedWDXo3hpwRGytbCEng3QFMqf6vLYQMegV2/lLguSY/lyGtqRsEgY+IZWKaY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=XGJPsma+; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="XGJPsma+" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id C05CF4E410F6; Wed, 5 Aug 2026 14:05:04 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 933BF602AB; Wed, 5 Aug 2026 14:05:04 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1F3A711C34B9D; Wed, 5 Aug 2026 16:04:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785938699; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=8QHlmUCfRMDCYm4XCbQfPD+NoA9p8cr7Dg0SwC6Cnx0=; b=XGJPsma+bnubqu0Y6npEobey93rSQjtfyKimTrfqnFkKWCI2D55QBPmGtJlUEIf7u79HA3 wXEsV9K45d5Uqe5XaUZHhHHNz1icvH6uAqIRawZ22GeMVzoYNLvhHIwmrQzy7AN3Ewmjex 24WPVMllDLyiQs93uqmL+okucUPonNeWIaNSusxLbf5hwcKeVjO1Qd24zzUyzVwbu0r96l AS5FOYEOmR/kEGmCqXy5ZiSar8yxCtv75Qr8ZJDHbePj2MRZyttApLe/mzveURS7plHeb3 YsCDBAqds8pkCOAyO7J7a9lIvORf0x1UZtwfeJl+oEF5B+b97QDpGK5eskUHJQ== From: Miquel Raynal To: "Michael Walle" Cc: "Pratyush Yadav" , "Takahiro Kuwano" , "Richard Weinberger" , "Vignesh Raghavendra" , "Nicolas Ferre" , "Alexandre Belloni" , "Claudiu Beznea" , "Steam Lin" , "Hsin-Yi Wang" , "Thomas Petazzoni" , , , Subject: Re: [PATCH 1/5] mtd: spi-nor: Refactor Read Status/Write Status support In-Reply-To: <87mrv2exwp.fsf@bootlin.com> (Miquel Raynal's message of "Tue, 04 Aug 2026 16:57:26 +0200") References: <20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com> <20260529-winbond-v7-1-spi-nor-rv-addition-v1-1-f3ae18502d5a@bootlin.com> <87mrv2exwp.fsf@bootlin.com> User-Agent: mu4e 1.12.12; emacs 30.2 Date: Wed, 05 Aug 2026 16:04:52 +0200 Message-ID: <87y0ekek8r.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Hello Michael, >>> +int spi_nor_read_srs(struct spi_nor *nor, u8 *sr1, u8 *sr2) >> >> nitpick, i think this is a weird name. But maybe it's just me. >> >> What if we'd just make the one status register as u32? I mean in the >> winbond datasheet it's called S7-S0 and S15-S8. That way we also >> don't need a two byte qe_mask. To optimize the standard usecase to >> poll the WIP bit, we could add a byte mask. I experimented a bit the u32 status register, I don't think it is a good idea. My target of improving the readability is completely defeated by the fact that: - all the callers need to add extra maths to explain what SR they want - endianness shall be handled, people always get it wrong (including me), so why bother if an array just makes the whole thing simpler? - 16-bit accesses get more convoluted, we need extra get_/put_unaligned_le32() calls and pack/unpack bytes in the hot path - 8-bit accesses imply an extensive use of FIELD_GET(GENMASK(),) macros, which make the whole fonction totally non obvious anymore. Whereas, a simple: if (sr2) *sr2 =3D foo; is self explanatory. I also do not really get the wish for a QE mask instead of a two bytes array. So I will rename the "srs" naming that you dislike, I will group the opcodes in a big structure, change the baseline default to match your suggestion and follow-up with the other minor comments, but I believe I'm going to avoid the u32 switch. Thanks, Miqu=C3=A8l