Re: [Question] Voltage droop from synchronized timer interrupts(tick) on many-core SoCs leads to system instability

[Thomas Gleixner <tglx@kernel.org>]

On Thu, Feb 05 2026 at 12:52, 连子涵 wrote:
> Given this constraint, we would greatly appreciate your insights on the following technical questions: 

Who is 'we'? You are hiding behind an anonymized email address and
completely fail to provide details about your secret sauce SoC.

> 1. Why does the timer interrupt path consume so much power and exhibit
>    such large instantaneous variations? Our power simulation shows that
>    the average power during timer interrupt handling is comparable to
>    Dhrystone benchmark.

Is that a serious question?

How should we know what makes your SoC design sensitive to it? You have
the tools which observe the problem, so you should be able to pin point
what the actual issue is, no?

> 3. Beyond skew_tick=1, are there other kernel mechanisms or runtime
>    strategies that could reduce the power impact of synchronized timer
>    events? Are there plans in future kernel versions to address this
>    issue more fundamentally—especially for many-core platforms?

Again. How should we address a problem which is only described by
hand-waving?  You completely fail to provide context and circumstances.

Provide a proper analysis that explains what the actual root cause is
and then we can debate whether that's solvable in software or not. Just
crying 'timer interrupt' is not even close to an analysis.

If there is a systematic problem somewhere then we are happy to look for
a solution, but without analysis and data we are not doing anything.

Just for the record: The Voltage droop issue is known for more a decade
and there have been solutions published way before your SoC was
designed. Aside of your (whatever it is) and some odd Ampere SoC none of
the contemporary multi-core designs even with hundreds of cores suffer
from this. Seems there are hardware architects out there who pay
attention to research.

Thanks,

        tglx