From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 662DBE54B; Sun, 1 Feb 2026 16:17:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769962671; cv=none; b=POto91JjjZxY1q+TK2M9lodyLOyoryTfvIZXY5OUhZyoqEWQptvTEcAH2vDrsFeJHj6s05+++Ankfk6fD7c7KmrpRkH+cxUy5dzhCudzPSpCM/B+T9zp3dZQ2GUMPSlHC2PJBEhGtua6iS20oXRgGmgaHfT+cYWET5P29IblrpM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769962671; c=relaxed/simple; bh=MPcc02T66lUJdgbvMWTdA6hvB5xZOJb9WklCiPV+SW0=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=keFeUVNMzZbK0B9ZYDdT+ZbGfZf+E6Nq/cXpxw8dTwQ9f65x5VbqkCr3Mk5pd9suwFr7Ecu+zircR4eX0W/ubE07LHpp7WF2eGo7el6sEuAxPPBm3Jl+M5wUIfRkqsQzzAPiW2lTaUHSLrHLhG6szTlXawvQurNkNRKph1mAIas= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DjF07Eoa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DjF07Eoa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1EA41C4CEF7; Sun, 1 Feb 2026 16:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769962670; bh=MPcc02T66lUJdgbvMWTdA6hvB5xZOJb9WklCiPV+SW0=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=DjF07Eoa2E7qVz65dYKHHvtpJmGMnpOlmxYtssmqBbdAGAP/0xevM++W0DIHX62Wh Szw775DlhGCzFmHCfSleDZcerIqah9dZ4dOeUjsxIBsAiNU6S+OUYJ2+4nwQ/2iw05 ZO9+0fP10UrYZ7/rgelyFd+HiBLV1daFGhsWyvy6oB4bGSgQgMh6T9z3gj90V4+yvW /9tIfYABwby3i5Go2yFwNncjbYcDLP154Pwnt8zZU8pX2erZl4fVIMP29mDrv1KJ4T dZSDCs7CRis5PpCv9sjTW1Xbh2gIVNKB2V7FLPpFtsIKI8PKkYVeCZG5L5Jk0D/Kmw NVpX4X9CrDjOA== From: Thomas Gleixner To: Huacai Chen , Icenowy Zheng Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Jiaxun Yang , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: Re: [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code In-Reply-To: References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> <20260131094547.455916-6-zhengxingda@iscas.ac.cn> Date: Sun, 01 Feb 2026 17:17:46 +0100 Message-ID: <87y0lcfnf9.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Sun, Feb 01 2026 at 10:33, Huacai Chen wrote: > Hi, Icenowy, > > On Sat, Jan 31, 2026 at 5:46=E2=80=AFPM Icenowy Zheng wrote: >> >> As the (kernel-internally) OF-based MIPS Loongson-3 systems can also >> have PCH LPC interrupt controller, add OF-based initialization code for >> the driver. > I think Patch-3/4/5 can be combined to a single one. No. #3 should be separate, but #4/#5 combined. It's easier to review the co= de rework and the new code separately. Thanks, tglx