From: Thomas Gleixner <tglx@linutronix.de>
To: Peter Zijlstra <peterz@infradead.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
Gabriele Monaco <gmonaco@redhat.com>,
Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
Michael Jeanson <mjeanson@efficios.com>,
Jens Axboe <axboe@kernel.dk>,
"Paul E. McKenney" <paulmck@kernel.org>,
"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
Florian Weimer <fweimer@redhat.com>,
Tim Chen <tim.c.chen@intel.com>,
TCMalloc Team <tcmalloc-eng@google.com>
Subject: Re: [patch 06/19] sched/mmcid: Prevent pointless work in mm_update_cpus_allowed()
Date: Fri, 17 Oct 2025 14:49:29 +0200 [thread overview]
Message-ID: <87y0p9zo9y.ffs@tglx> (raw)
In-Reply-To: <20251017111223.GD4067720@noisy.programming.kicks-ass.net>
On Fri, Oct 17 2025 at 13:12, Peter Zijlstra wrote:
> On Wed, Oct 15, 2025 at 07:29:34PM +0200, Thomas Gleixner wrote:
>
>> + if (!mm || READ_ONCE(mm->mm_cid.nr_cpus_allowed) == nr_cpu_ids)
>> return;
>
> FWIW this doesn't work on architectures that change their
> cpu_possible_mask around (eg. Power).
No. Power does not change it after boot either. Half of the kernel would
explode if that'd be the case.
Thanks,
tglx
next prev parent reply other threads:[~2025-10-17 12:49 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 17:29 [patch 00/19] sched: Rewrite MM CID management Thomas Gleixner
2025-10-15 17:29 ` [patch 01/19] sched/mmcid: Revert the complex " Thomas Gleixner
2025-10-15 17:29 ` [patch 02/19] sched/mmcid: Use proper data structures Thomas Gleixner
2025-10-15 17:29 ` [patch 03/19] sched/mmcid: Cacheline align MM CID storage Thomas Gleixner
2025-10-15 17:29 ` [patch 04/19] sched: Fixup whitespace damage Thomas Gleixner
2025-10-15 17:29 ` [patch 05/19] sched/mmcid: Move scheduler code out of global header Thomas Gleixner
2025-10-15 17:29 ` [patch 06/19] sched/mmcid: Prevent pointless work in mm_update_cpus_allowed() Thomas Gleixner
2025-10-17 11:12 ` Peter Zijlstra
2025-10-17 12:49 ` Thomas Gleixner [this message]
2025-10-17 17:58 ` Peter Zijlstra
2025-10-17 18:19 ` Peter Zijlstra
2025-10-19 20:32 ` Thomas Gleixner
2025-10-20 8:22 ` Peter Zijlstra
2025-10-21 18:25 ` Thomas Gleixner
2025-10-15 17:29 ` [patch 07/19] cpumask: Introduce cpumask_or_weight() Thomas Gleixner
2025-10-15 17:41 ` Yury Norov
2025-10-15 18:06 ` Yury Norov
2025-10-21 20:21 ` Thomas Gleixner
2025-10-21 19:34 ` Thomas Gleixner
2025-10-15 17:29 ` [patch 08/19] sched/mmcid: Use cpumask_or_weight() Thomas Gleixner
2025-10-15 17:29 ` [patch 09/19] sched/mmcid: Convert mm CID mask to a bitmap Thomas Gleixner
2025-10-15 17:29 ` [patch 10/19] signal: Move MMCID exit out of sighand lock Thomas Gleixner
2025-10-15 17:29 ` [patch 11/19] sched/mmcid: Move initialization out of line Thomas Gleixner
2025-10-15 17:29 ` [patch 12/19] sched/mmcid: Provide precomputed maximal value Thomas Gleixner
2025-10-15 17:29 ` [patch 13/19] sched/mmcid: Serialize sched_mm_cid_fork()/exit() with a mutex Thomas Gleixner
2025-10-15 17:29 ` [patch 14/19] sched/mmcid: Introduce per task/CPU ownership infrastrcuture Thomas Gleixner
2025-10-15 17:29 ` [patch 15/19] sched/mmcid: Provide new scheduler CID mechanism Thomas Gleixner
2025-10-15 17:29 ` [patch 16/19] sched/mmcid: Provide CID ownership mode fixup functions Thomas Gleixner
2025-10-20 6:34 ` Thomas Gleixner
2025-10-20 9:13 ` Peter Zijlstra
2025-10-20 9:16 ` Peter Zijlstra
2025-10-20 9:27 ` Peter Zijlstra
2025-10-21 18:27 ` Thomas Gleixner
2025-10-15 17:29 ` [patch 17/19] irqwork: Move data struct to a types header Thomas Gleixner
2025-10-15 17:29 ` [patch 18/19] sched/mmcid: Implement deferred mode change Thomas Gleixner
2025-10-15 17:30 ` [patch 19/19] sched/mmcid: Switch over to the new mechanism Thomas Gleixner
2025-10-17 7:09 ` [patch 00/19] sched: Rewrite MM CID management Thomas Gleixner
2025-10-17 11:31 ` Florian Weimer
2025-10-17 12:56 ` Thomas Gleixner
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