[PATCH] irqchip/loongson-liointc: Set different ISRs for different cores

[PATCH] irqchip/loongson-liointc: Set different ISRs for different cores

[Huacai Chen]

In the liointc hardware, there are different ISRs for different cores.
We always use core#0's ISR before but has no problem, it is because the
interrupts are routed to core#0 by default. If we change the routing,
we should set correct ISRs for different cores.

Cc: <stable@vger.kernel.org>
Signed-off-by: Tianli Xiong <xiongtianli@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/irq-loongson-liointc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index e4b33aed1c97..7c4fe7ab4b83 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -28,7 +28,7 @@
 
 #define LIOINTC_INTC_CHIP_START	0x20
 
-#define LIOINTC_REG_INTC_STATUS	(LIOINTC_INTC_CHIP_START + 0x20)
+#define LIOINTC_REG_INTC_STATUS(core)	(LIOINTC_INTC_CHIP_START + 0x20 + (core) * 8)
 #define LIOINTC_REG_INTC_EN_STATUS	(LIOINTC_INTC_CHIP_START + 0x04)
 #define LIOINTC_REG_INTC_ENABLE	(LIOINTC_INTC_CHIP_START + 0x08)
 #define LIOINTC_REG_INTC_DISABLE	(LIOINTC_INTC_CHIP_START + 0x0c)
@@ -217,7 +217,7 @@ static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
 		goto out_free_priv;
 
 	for (i = 0; i < LIOINTC_NUM_CORES; i++)
-		priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
+		priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS(i);
 
 	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
 		priv->handler[i].parent_int_map = parent_int_map[i];
-- 
2.43.0

Re: [PATCH] irqchip/loongson-liointc: Set different ISRs for different cores

[Thomas Gleixner]

On Wed, Jun 12 2024 at 15:01, Huacai Chen wrote:
> In the liointc hardware, there are different ISRs for different cores.

I have no idea what ISR means in that context. Can you please spell it
out with proper words so that people not familiar with the details can
understand it?

> We always use core#0's ISR before but has no problem, it is because the
> interrupts are routed to core#0 by default. If we change the routing,
> we should set correct ISRs for different cores.

We do nothing. The code does.

See https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog

> Cc: <stable@vger.kernel.org>
> Signed-off-by: Tianli Xiong <xiongtianli@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

This Signed-off-by chain is wrong. If Tianli is the author then this
needs a From: Tianli in the changelog. If you developed it together then
this lacks a Co-developed-by tag.

See Documentation/process/

Thanks,

        tglx

Re: [PATCH] irqchip/loongson-liointc: Set different ISRs for different cores

[Huacai Chen]

Hi, Thomas,

On Sat, Jun 22, 2024 at 2:40 AM Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Wed, Jun 12 2024 at 15:01, Huacai Chen wrote:
> > In the liointc hardware, there are different ISRs for different cores.
>
> I have no idea what ISR means in that context. Can you please spell it
> out with proper words so that people not familiar with the details can
> understand it?
ISR means "Interrupt Status Register" here, I will improve the wording.

>
> > We always use core#0's ISR before but has no problem, it is because the
> > interrupts are routed to core#0 by default. If we change the routing,
> > we should set correct ISRs for different cores.
>
> We do nothing. The code does.
>
> See https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog
Let me try my best...

>
> > Cc: <stable@vger.kernel.org>
> > Signed-off-by: Tianli Xiong <xiongtianli@loongson.cn>
> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>
> This Signed-off-by chain is wrong. If Tianli is the author then this
> needs a From: Tianli in the changelog. If you developed it together then
> this lacks a Co-developed-by tag.
Yes, here we lack a Co-developed-by, thanks.

Huacai

>
> See Documentation/process/
>
> Thanks,
>
>         tglx