Re: [PATCH V14 13/15] irqchip: Add LoongArch CPU interrupt controller support

Marc Zyngier
2022-07-07T12:44:55Z

On Sun, 03 Jul 2022 09:45:30 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> From: Huacai Chen <chenhuacai@loongson.cn>
>
> LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
> controller that described in Section 7.4 of "LoongArch Reference Manual,
> Vol 1". For more information please refer Documentation/loongarch/irq-
> chip-model.rst.
>
> LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
> (Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
> created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
> bits, so we define get_xxx_irq() for them.

I really dislike this practice. Even if these 3 interrupts are well
known (their hwirqs are set in stone), you should be able to directly
create the interrupt from the rest of the kernel code.

All you have to do is to expose the fwnode_handle in the arch code
(just like you do for other interrupt controllers), retrieve the
domain and perform the mapping. No need for any extra arch-specific
API in the irqchip controller.

It would also be good to mention that this irqchip driver also probes
the all the rest of the interrupt hierarchy.

Thanks,

M.

--
Without deviation from the norm, progress is not possible.