Re: [PATCH 2/5] irqchip/qcom-pdc: Kill non-wakeup irqdomain

[Marc Zyngier <maz@kernel.org>]

On Mon, 28 Feb 2022 19:29:41 +0000,
"Maulik Shah (mkshah)" <quic_mkshah@quicinc.com> wrote:
> 
> Hi,
> 
> On 2/24/2022 3:42 PM, Marc Zyngier wrote:
> > A careful look at the way the PDC driver works shows that:
> > 
> > - all interrupts are in the same space
> > - all interrupts are treated the same
> > 
> > And yet the driver creates two domains based on whether
> > the interrupt gets mapped directly or from the pinctrl code,
> > which is obviously a waste of resources.
> The GPIO is kept under separate domain to handle extra configuration
> for wake GPIO handling.

Which extra configuration? The irq_chip structure is the same, the
translation is the same, the GIC mapping is the same, and the select
method only serves to select between two irq domains that do the same
thing.

So please point me to what the difference is.

> 
> On targets like SM8150/SM8250 each wake up capable GPIO (if totan n)
> line has dedicated parent PDC irq (if total m, n = m) associated with
> it.
> However on targets like sdx55 PDC has muxes where each wake GPIO (if
> total n) line goes through each PDC muxes (if total m, n > m) and
> any of these muxes can be used to route any one GPIO to PDC (and
> parent GIC) but unlike other targets it doesn't have one to one
> mapping for GPIO to GIC interrupt.
> So this will need to be kept as is to support sdx55 target.

As far as I can tell, the current code doesn't have any support for
this. And if there is a mux involved in the interrupt routing, this
should be something entierly separate, as the current code is strictly
hierarchical.

What am I missing?

	M.

-- 
Without deviation from the norm, progress is not possible.