From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932173AbcEKPXi (ORCPT ); Wed, 11 May 2016 11:23:38 -0400 Received: from mga14.intel.com ([192.55.52.115]:19644 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751338AbcEKPXh (ORCPT ); Wed, 11 May 2016 11:23:37 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,608,1455004800"; d="scan'208";a="101310604" From: jeremy.compostella@intel.com (Compostella, Jeremy) To: Ingo Molnar Cc: "H. Peter Anvin" , Subject: Re: [PATCH] x86: tsc: Add missing Cherrytrail frequency to the table References: <877ff0vg7y.fsf@intel.com> Date: Wed, 11 May 2016 17:23:34 +0200 In-Reply-To: <877ff0vg7y.fsf@intel.com> (Jeremy Compostella's message of "Wed, 11 May 2016 16:09:37 +0200") Message-ID: <87y47gty89.fsf@intel.com> User-Agent: Gnus/5.130012 (Ma Gnus v0.12) Emacs/25.0.50 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4 means that the CPU reference clock runs at 80MHz. Add this missing frequency to the table. Signed-off-by: Jeremy Compostella --- arch/x86/kernel/tsc_msr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index 6aa0f4d..ab271a7 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -23,6 +23,7 @@ #include /* CPU reference clock frequency: in KHz */ +#define FREQ_80 80000 #define FREQ_83 83200 #define FREQ_100 99840 #define FREQ_133 133200 @@ -56,6 +57,9 @@ static struct freq_desc freq_desc_tables[] = { { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } }, /* ANN */ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, + /* AIRMONT */ + { 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80, + 0, 0, 0 } }, }; static int match_cpu(u8 family, u8 model) -- 1.9.1