From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A266E2264A9 for ; Tue, 5 May 2026 20:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778011738; cv=none; b=FEV9HllU/Qi+Iuq7p6p+PJjEYPzUgORUTa2ARjDujleSIayYFBXIF4E97ZdK3EN2pYpNOuR9aWOw+HazWLQe8UWOTMbVywgKpwkYVKFAlv8nM5dmg9frirqUTQl9iheJtRaoQ6g/vNpknGfhUrkFpfDg5akBqgByBISQ43+x1oQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778011738; c=relaxed/simple; bh=/j11J9M2rpjHFDo2P3PpYGg75ACUlpOX6HbyyxFh7nk=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=Qdx00iokALhhizmTgh/D+PfzHOIhNNipbj5+0mSt4V7ccfXvzh1EFGAvHm9Clnz0lwKlxwXeAliz1wueVr0Ev0+JS03o1Tz62KJEAOsSAujmrumxLRWglf29aOn8cI6U1qq0Xto98hnbyW1/6MUuzb2ENT8dIBZXf2SdeAeIjJc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eocsxk8/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eocsxk8/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0935C2BCB4; Tue, 5 May 2026 20:08:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778011738; bh=/j11J9M2rpjHFDo2P3PpYGg75ACUlpOX6HbyyxFh7nk=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=eocsxk8/k0flO75+vYiaiRdFsHmYWsbGcX1ILS8p9jwmitTwEiStHDi+9MuFyzSvp kJI/WG/HeTBKGhzh3fvWcNYRmmFJ5IhSdG/LxxGliTZo5ctiCxiYrWEn7PVnWu+sRD eTdMr1LftCcqow29DhBAZBwQsQUdJhHLG0PEci07XLjMOtH2JU1QwykZJ9fRluqigN h7lBS7JMOQitGZ/qZQnVapq3Kj1E9scCekC9fL+SAX8YGnC2gbYm4djsGPfhPNRyYa ApNWchCJhBndTET24wXpzEm+MRiYxdDSHfJXhFODQ3zPOVkrrROIqSVqN8eTMV0npD a3v8U68ShHQpA== From: Thomas Gleixner To: Sascha Bischoff , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Cc: nd , Lorenzo Pieralisi , Marc Zyngier Subject: Re: [PATCH 2/3] irqchip/gic-v5: Allow for nr_irqs > 1 for LPI alloc and teardown In-Reply-To: <20260430153352.3654325-3-sascha.bischoff@arm.com> References: <20260430153352.3654325-1-sascha.bischoff@arm.com> <20260430153352.3654325-3-sascha.bischoff@arm.com> Date: Tue, 05 May 2026 22:08:55 +0200 Message-ID: <87zf2dwre0.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Thu, Apr 30 2026 at 15:34, Sascha Bischoff wrote: > Formerly the LPI allocaion and freeing was handled by the domains > built on top of the LPI domain, and hence the LPI to use was passed in > from the child domain. This mandadated that LPI allocation and freeing > was done one at a time, rather than for a range of interrupts in one > go. > > Now that the underlying restriction has been removed and all LPI > tracking happens within the LPI domain itself, drop the requirement to > allocate and free LPIs one-by-one. While we're at it, clean up the > IPI allocation to request all LPIs in one go, rather than requesting > them one at a time. > > Incidentally, this fixes a unwind bug for IPIs where previously > allocated entries were not unwound on a failed parent allocation. See previous reply > Signed-off-by: Sascha Bischoff > --- > drivers/irqchip/irq-gic-v5.c | 70 +++++++++++++++++++----------------- > 1 file changed, 38 insertions(+), 32 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c > index a3c9eaa8ff486..61a70fe48bc32 100644 > --- a/drivers/irqchip/irq-gic-v5.c > +++ b/drivers/irqchip/irq-gic-v5.c > @@ -800,17 +800,16 @@ static void gicv5_irq_lpi_domain_free(struct irq_domain *domain, unsigned int vi > unsigned int nr_irqs) > { > struct irq_data *d; > + int i; > > - if (WARN_ON_ONCE(nr_irqs != 1)) > - return; > - > - d = irq_domain_get_irq_data(domain, virq); > - > + for (i = 0; i < nr_irqs; i++) { for (unsigned int = 0; .... > + d = irq_domain_get_irq_data(domain, virq + i); s/virq/ and then make for (unsigned int = 0; ....; i++, virq++) > static int gicv5_irq_lpi_domain_alloc(struct irq_domain *domain, unsigned int virq, > @@ -818,32 +817,38 @@ static int gicv5_irq_lpi_domain_alloc(struct irq_domain *domain, unsigned int vi > { > irq_hw_number_t hwirq; > struct irq_data *irqd; > - int ret; > - > - if (WARN_ON_ONCE(nr_irqs != 1)) > - return -EINVAL; > + int ret, i; unsigned int i; > static const struct irq_domain_ops gicv5_irq_lpi_domain_ops = { > @@ -871,11 +876,11 @@ static int gicv5_irq_ipi_domain_alloc(struct irq_domain *domain, unsigned int vi > struct irq_data *irqd; > int ret, i; > > - for (i = 0; i < nr_irqs; i++) { > - ret = irq_domain_alloc_irqs_parent(domain, virq + i, 1, NULL); > - if (ret) > - return ret; > + ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); > + if (ret) > + return ret; > > + for (i = 0; i < nr_irqs; i++) { for (unsigned int i .... Thanks, tglx