From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mout01.posteo.de (mout01.posteo.de [185.67.36.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 653C0361DA8 for ; Fri, 27 Feb 2026 17:00:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.67.36.65 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772211614; cv=none; b=sp8WHpYUCegqOZw/stT2lULWrYTIICAXVc0QTVctLA0keNiYR5S+eDE0TDAkrguwnwHfklZ7tP6fM9XGvKWn3NSUeqbMmZCCV6381P7bYWkOB6hRRY338EHKZJiTGR6VXic3xKMJ8k15ncUNpUnuioDtA7x3ef7yt6GrfzTaQaw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772211614; c=relaxed/simple; bh=oC2Zs14lpqc+KoWFpjTryVFAJSLb63H0KdFepDU/dvI=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=ZD9YKaQWymCUdEE0SQRBx7qBnwiS2yHMe+H0czsSZQa1qNHIVgYUz4Z2N9E/cAMEqNajsarLez8wbPqY4fjBNRgObAkHxkHrJOP3KR71JTX4dxaW3X2Q1evTFDfck1CYROjTerbA8ZfJO73qqx6Rv8odvzmAOyt5t6aU5khthMo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=posteo.net; spf=pass smtp.mailfrom=posteo.net; dkim=pass (2048-bit key) header.d=posteo.net header.i=@posteo.net header.b=T324cFJM; arc=none smtp.client-ip=185.67.36.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=posteo.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=posteo.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=posteo.net header.i=@posteo.net header.b="T324cFJM" Received: from submission (posteo.de [185.67.36.169]) by mout01.posteo.de (Postfix) with ESMTPS id 70DCC240029 for ; Fri, 27 Feb 2026 18:00:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=posteo.net; s=2017; t=1772211604; bh=29xGwZx4QmtZUrfPtkG3nKCYS3+MgHmL/NsrLP4T1A8=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version:Content-Type: From; b=T324cFJML0YvQ2TOys9nnjk9fwDx8Te/HibiDWHLIVeZ0VUjfkt+YB8F+fFttRp2c hJWgtfhjqFYfUiIuPSztPeq0xx1frDojLy8adNOFaEXZoxC9qe4a+V7oH+UAqAQ6U9 egsD33xTLHanYHWn9NNnN5Ld/1U3NNRKnXLiw29iQMzF01db5TCyPRF8B8DRh8Uv8q 5DLDw2z3BofmiXHUCl3m75ZicYwHg7z+9vEiPZot+dMSbmnX43q11JNIvAV8pYERZF /Ry2MkUIUwCBnF+708HAghE++wGnJQ2MmC93/RFOePv/sd1jONmlnMNr6tdWcfgbg6 UxLawYm9xfHvQ== Received: from customer (localhost [127.0.0.1]) by submission (posteo.de) with ESMTPSA id 4fMvhK3Zmfz9rxN; Fri, 27 Feb 2026 18:00:01 +0100 (CET) From: Charalampos Mitrodimas To: Geraldo Nascimento Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Dragan Simic , linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 4/4] PCI: rockchip-ep: do not attempt 5.0 GT/s retraining In-Reply-To: References: Date: Fri, 27 Feb 2026 17:00:03 +0000 Message-ID: <87zf4ujf5b.fsf@posteo.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Geraldo Nascimento writes: > Drop the 5.0 GT/s Link Speed retraining code block from Rockchip PCIe > header definitions. The reason is that Shawn Lin from Rockchip has > reiterated that there may be danger of "catastrophic failure" in > using their PCIe with 5.0 GT/s speeds. Patch body says "header definitions" but the change is to the drivers' source. Maybe you need to reword in a way that is clear as to what happened? Cheers! > > While Rockchip has done so informally without issuing a proper > errata, and the particulars are thus unknown, this may cause data > loss or worse. > > This change is corroborated by RK3399 official datasheet [1], which > states maximum link speed for this platform is 2.5 GT/s. > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf > > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ > Cc: stable@vger.kernel.org > Reported-by: Dragan Simic > Reported-by: Shawn Lin > Signed-off-by: Geraldo Nascimento > --- > drivers/pci/controller/pcie-rockchip-ep.c | 13 ------------- > 1 file changed, 13 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > index 799461335762..9ebc227a1ef8 100644 > --- a/drivers/pci/controller/pcie-rockchip-ep.c > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > @@ -553,19 +553,6 @@ static void rockchip_pcie_ep_link_training(struct work_struct *work) > if (ret) > goto again; > > - /* > - * Check the current speed: if gen2 speed was requested and we are not > - * at gen2 speed yet, retrain again for gen2. > - */ > - val = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL); > - if (!PCIE_LINK_IS_GEN2(val) && rockchip->link_gen == 2) { > - /* Enable retrain for gen2 */ > - rockchip_pcie_ep_retrain_link(rockchip); > - readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, > - val, PCIE_LINK_IS_GEN2(val), 50, > - LINK_TRAIN_TIMEOUT); > - } > - > /* Check again that the link is up */ > if (!rockchip_pcie_ep_link_up(rockchip)) > goto again;