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From: Thomas Gleixner <tglx@linutronix.de>
To: Marek Szyprowski <m.szyprowski@samsung.com>,
	LKML <linux-kernel@vger.kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Gabriele Monaco <gmonaco@redhat.com>,
	Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
	Michael Jeanson <mjeanson@efficios.com>,
	Jens Axboe <axboe@kernel.dk>,
	"Paul E. McKenney" <paulmck@kernel.org>,
	"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
	Florian Weimer <fweimer@redhat.com>,
	Tim Chen <tim.c.chen@intel.com>,
	Yury Norov <yury.norov@gmail.com>,
	Shrikanth Hegde <sshegde@linux.ibm.com>,
	Nathan Chancellor <nathan@kernel.org>
Subject: Re: [patch V5 09/20] cpumask: Cache num_possible_cpus()
Date: Sat, 22 Nov 2025 16:36:28 +0100	[thread overview]
Message-ID: <87zf8ehyf7.ffs@tglx> (raw)
In-Reply-To: <89c7106e-a431-443a-9527-3d5fbce77fe1@samsung.com>

On Fri, Nov 21 2025 at 23:56, Marek Szyprowski wrote:
> Reverting it on top of linux-next fixes the issue. Let me know how can I 
> help debugging it.

Can you test the fix below please?

Thanks,

        tglx
---
Subject: cpu: Initialize __num_possible_cpus correctly
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sat, 22 Nov 2025 16:19:18 +0100

The variable to cache the number of possible CPUs is initialized to NR_CPUS
at build time, but that's only correct when cpu_possible_mask is
initialized with CPU_BITS_ALL. That's only the case on PARISC.

On x86 and some other architectures this does not matter because they
initialize cpu_possible_mask via init_cpu_possible() which does a proper
weight calculation. Though on architectures which do not, this results
in a completely wrong cached value 'NR_CPUS + actual possible CPUs'.

Initialize it correctly to 0 when CONFIG_INIT_ALL_POSSIBLE=n and move the
NR_CPUS initialization into the PARISC specific section.

Fixes: d0f23ccf6ba9 ("cpumask: Cache num_possible_cpus()")
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Closes: https://lore.kernel.org/all/89c7106e-a431-443a-9527-3d5fbce77fe1@samsung.com
Closes: https://lore.kernel.org/all/20251122002755.GA2682494@ax162
---
 kernel/cpu.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -3085,10 +3085,13 @@ EXPORT_SYMBOL(cpu_all_bits);
 #ifdef CONFIG_INIT_ALL_POSSIBLE
 struct cpumask __cpu_possible_mask __ro_after_init
 	= {CPU_BITS_ALL};
+unsigned int __num_possible_cpus __ro_after_init = NR_CPUS;
 #else
 struct cpumask __cpu_possible_mask __ro_after_init;
+unsigned int __num_possible_cpus __ro_after_init;
 #endif
 EXPORT_SYMBOL(__cpu_possible_mask);
+EXPORT_SYMBOL(__num_possible_cpus);
 
 struct cpumask __cpu_online_mask __read_mostly;
 EXPORT_SYMBOL(__cpu_online_mask);
@@ -3108,9 +3111,6 @@ EXPORT_SYMBOL(__cpu_dying_mask);
 atomic_t __num_online_cpus __read_mostly;
 EXPORT_SYMBOL(__num_online_cpus);
 
-unsigned int __num_possible_cpus __ro_after_init = NR_CPUS;
-EXPORT_SYMBOL(__num_possible_cpus);
-
 void init_cpu_present(const struct cpumask *src)
 {
 	cpumask_copy(&__cpu_present_mask, src);

  reply	other threads:[~2025-11-22 15:36 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-19 17:26 [patch V5 00/20] sched: Rewrite MM CID management Thomas Gleixner
2025-11-19 17:26 ` [patch V5 01/20] sched/mmcid: Revert the complex " Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 02/20] sched/mmcid: Use proper data structures Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 03/20] sched/mmcid: Cacheline align MM CID storage Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 04/20] sched: Fixup whitespace damage Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 05/20] sched/mmcid: Move scheduler code out of global header Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 06/20] sched/mmcid: Prevent pointless work in mm_update_cpus_allowed() Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 07/20] cpumask: Introduce cpumask_weighted_or() Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:26 ` [patch V5 08/20] sched/mmcid: Use cpumask_weighted_or() Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 09/20] cpumask: Cache num_possible_cpus() Thomas Gleixner
2025-11-20 11:20   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-21 22:56   ` [patch V5 09/20] " Marek Szyprowski
2025-11-22 15:36     ` Thomas Gleixner [this message]
2025-11-22 16:24       ` Marek Szyprowski
2025-11-22 19:09         ` Paul E. McKenney
2025-11-23 19:03       ` [tip: core/rseq] cpu: Initialize __num_possible_cpus correctly tip-bot2 for Thomas Gleixner
2025-11-22 18:47     ` [patch V5 09/20] cpumask: Cache num_possible_cpus() Paul E. McKenney
2025-11-22 19:10       ` Thomas Gleixner
2025-11-22  0:27   ` Nathan Chancellor
2025-11-26  4:36   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 10/20] sched/mmcid: Convert mm CID mask to a bitmap Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 11/20] signal: Move MMCID exit out of sighand lock Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 12/20] sched/mmcid: Move initialization out of line Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 13/20] sched/mmcid: Provide precomputed maximal value Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 14/20] sched/mmcid: Serialize sched_mm_cid_fork()/exit() with a mutex Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 15/20] sched/mmcid: Introduce per task/CPU ownership infrastructure Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 16/20] sched/mmcid: Provide new scheduler CID mechanism Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 17/20] sched/mmcid: Provide CID ownership mode fixup functions Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 18/20] irqwork: Move data struct to a types header Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 19/20] sched/mmcid: Implement deferred mode change Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` tip-bot2 for Thomas Gleixner
2025-11-19 17:27 ` [patch V5 20/20] sched/mmcid: Switch over to the new mechanism Thomas Gleixner
2025-11-20 11:19   ` [tip: core/rseq] " tip-bot2 for Thomas Gleixner
2025-11-22  0:43   ` [patch V5 20/20] " Nathan Chancellor
2025-11-22 15:02     ` Thomas Gleixner
2025-11-22 16:54       ` Shrikanth Hegde
2025-11-23 19:03       ` [tip: core/rseq] sched/mmcid: Ensure that per CPU threshold is > 0 tip-bot2 for Thomas Gleixner
2025-11-26  4:36   ` [tip: core/rseq] sched/mmcid: Switch over to the new mechanism tip-bot2 for Thomas Gleixner
2026-01-28  0:01 ` [patch V5 00/20] sched: Rewrite MM CID management Ihor Solodrai
2026-01-28  8:46   ` Peter Zijlstra
2026-01-28 11:57   ` Thomas Gleixner
2026-01-28 12:58     ` Shrikanth Hegde
2026-01-28 13:56       ` Thomas Gleixner
2026-01-28 22:24         ` Thomas Gleixner
2026-01-28 22:33           ` Ihor Solodrai
2026-01-28 23:08             ` Ihor Solodrai
2026-01-29 17:06               ` Thomas Gleixner

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