[patch V3 03/20] sched/mmcid: Cacheline align MM CID storage

Thomas Gleixner
2025-10-29T13:09:01Z

Both the per CPU storage and the data in mm_struct are heavily used in
context switch. As they can end up next to other frequently modified data,
they are subject to false sharing.

Make them cache line aligned.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
include/linux/rseq_types.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

--- a/include/linux/rseq_types.h
+++ b/include/linux/rseq_types.h
@@ -112,7 +112,7 @@ struct sched_mm_cid {
*/
struct mm_cid_pcpu {
unsigned int cid;
-};
+}____cacheline_aligned_in_smp;

/**
* struct mm_mm_cid - Storage for per MM CID data
@@ -126,7 +126,7 @@ struct mm_mm_cid {
struct mm_cid_pcpu __percpu *pcpu;
unsigned int nr_cpus_allowed;
raw_spinlock_t lock;
-};
+}____cacheline_aligned_in_smp;
#else /* CONFIG_SCHED_MM_CID */
struct mm_mm_cid { };
struct sched_mm_cid { };