From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBA7FC433ED for ; Tue, 13 Apr 2021 10:43:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD47C613B8 for ; Tue, 13 Apr 2021 10:43:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245752AbhDMKnd (ORCPT ); Tue, 13 Apr 2021 06:43:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:46164 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229686AbhDMKnb (ORCPT ); Tue, 13 Apr 2021 06:43:31 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 65A9E61278; Tue, 13 Apr 2021 10:43:12 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lWGVh-007D8j-AI; Tue, 13 Apr 2021 11:43:09 +0100 Date: Tue, 13 Apr 2021 11:43:08 +0100 Message-ID: <87zgy2mpmr.wl-maz@kernel.org> From: Marc Zyngier To: 414777006@qq.com Cc: tglx@linutronix.de, linux-kernel@vger.kernel.org, Mengguang Peng Subject: Re: [PATCH] Fixed: ARM64 GIC ITS could not resume from suspend In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: 414777006@qq.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, pengmengguang@phytium.com.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 13 Apr 2021 07:40:10 +0100, 414777006@qq.com wrote: > > From: Mengguang Peng > > - After ITS suspend, in the ATF(arm-trusted-firmware), > gicv3_rdistif_init_restore() just restore GICR_CTLR.Enable_LPIs bit > of boot cpu. > > - In its_cpu_init_lpis() of kernel, gic_data_rdist()->lpi_enable > will block setting GICR_CTLR_ENABLE_LPIS bit of the other CPUs > when ITS resume after suspend. > > Signed-off-by: Mengguang Peng > --- > drivers/irqchip/irq-gic-v3-its.c | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > index ed46e60..8167397 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -4777,7 +4777,7 @@ static int its_save_disable(void) > static void its_restore_enable(void) > { > struct its_node *its; > - int ret; > + int ret, cpu; > > raw_spin_lock(&its_lock); > list_for_each_entry(its, &its_nodes, entry) { > @@ -4831,6 +4831,22 @@ static void its_restore_enable(void) > GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) > its_cpu_init_collection(its); > } > + > + /* > + * Enable LPIs: firmware just restore GICR_CTLR.Enable_LPIs > + * of boot cpu, the other CPUs also should be restore. > + */ > + for_each_online_cpu(cpu) { > + void __iomem *rbase = gic_data_rdist_cpu(cpu)->rd_base; > + u32 val; > + > + /* Enable LPIs */ > + val = readl_relaxed(rbase + GICR_CTLR); > + if (val) > + continue; > + val |= GICR_CTLR_ENABLE_LPIS; > + writel_relaxed(val, rbase + GICR_CTLR); > + } > raw_spin_unlock(&its_lock); > } This looks completely flawed. If GICR_CTLR.Enable_LPIs is clear on resume, how can you trust the rest of the bits in the register? How can you trust *any* register in the redistributor? And what makes you think it is valid or safe to blindly enable LPIs without even checking whether they were enabled the first place? I will reiterate my take on this: if the firmware messes with the RD on suspend, please address the problem in the firmware so that the RDs are correctly restored on each CPU. Thanks, M. -- Without deviation from the norm, progress is not possible.