From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: eranian@google.com, acme@redhat.com, mingo@kernel.org,
mpe@ellerman.id.au, linux-kernel@vger.kernel.org,
jolsa@kernel.org, namhyung@kernel.org,
vitaly.slobodskoy@intel.com, pavel.gerasimov@intel.com,
ak@linux.intel.com
Subject: Re: [RESEND PATCH V5 1/2] perf/core: Add new branch sample type for HW index of raw branch records
Date: Mon, 20 Jan 2020 11:50:59 -0500 [thread overview]
Message-ID: <88802724-aa70-23bc-b2c8-a7a34aa3dfe5@linux.intel.com> (raw)
In-Reply-To: <20200120092300.GK14879@hirez.programming.kicks-ass.net>
On 1/20/2020 4:23 AM, Peter Zijlstra wrote:
> On Thu, Jan 16, 2020 at 07:57:56AM -0800, kan.liang@linux.intel.com wrote:
>
>> struct perf_branch_stack {
>> __u64 nr;
>> + __u64 hw_idx;
>> struct perf_branch_entry entries[0];
>> };
>
> The above and below order doesn't match.
>
>> @@ -849,7 +853,11 @@ enum perf_event_type {
>> * char data[size];}&& PERF_SAMPLE_RAW
>> *
>> * { u64 nr;
>> - * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
>> + * { u64 from, to, flags } lbr[nr];
>> + *
>> + * # only available if PERF_SAMPLE_BRANCH_HW_INDEX is set
>> + * u64 hw_idx;
>> + * } && PERF_SAMPLE_BRANCH_STACK
>
> That wants to be written as:
>
> { u64 nr;
> { u64 from, to, flags; } entries[nr];
> { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
> } && PERF_SAMPLE_BRANCH_STACK
>
> But the big question is; why isn't it:
>
> { u64 nr;
> { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
> { u64 from, to, flags; } entries[nr];
> } && PERF_SAMPLE_BRANCH_STACK
>
> to match the struct perf_branch_stack order. Having that variable sized
> entry in the middle just seems weird.
Usually, new data should be output to the end of a sample.
The comments and codes are all based on that way.
However, the entries[0] is sized entry, so I have to put the hw_idx
before entry. It makes the inconsistency. Sorry for the confusion caused.
I will fix it in V6.
Thanks,
Kan
>
>> *
>> * { u64 abi; # enum perf_sample_regs_abi
>> * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
next prev parent reply other threads:[~2020-01-20 16:51 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-16 15:57 [RESEND PATCH V5 0/2] Stitch LBR call stack (kernel) kan.liang
2020-01-16 15:57 ` [RESEND PATCH V5 1/2] perf/core: Add new branch sample type for HW index of raw branch records kan.liang
2020-01-20 9:23 ` Peter Zijlstra
2020-01-20 16:50 ` Liang, Kan [this message]
2020-01-20 20:24 ` Peter Zijlstra
2020-01-20 20:47 ` Liang, Kan
2020-01-21 9:32 ` Stephane Eranian
2020-01-21 15:02 ` Liang, Kan
2020-01-16 15:57 ` [RESEND PATCH V5 2/2] perf/x86/intel: Output LBR TOS information kan.liang
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