Re: PROBLEM: Network hang: "eth0: Tx timed out (f0080), is buffer full?" (Plain)

Jon Mason
2004-12-17T20:52:37Z

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Richard,
Please give the patch below a try (I've also attached it for you
convienance), and send me the dmesg output from the next time you hit
the error.

--- dl2k.c 2004-09-10 10:46:34.000000000 -0500
+++ /tmp/dl2k.c 2004-12-17 14:37:40.644124080 -0600
@@ -565,8 +565,9 @@ rio_tx_timeout (struct net_device *dev)
{
long ioaddr = dev->base_addr;

- printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
- dev->name, readl (ioaddr + TxStatus));
+ printk (KERN_INFO "%s: Tx timed out (%4.4x) %d %d %x %x\n",
+ dev->name, readl (ioaddr + TxStatus), np->cur_tx, np->cur_rx,
+ readl (ioaddr + DMACtrl), readw(ioaddr + IntEnable));
rio_free_tx(dev, 0);
dev->if_port = 0;
dev->trans_start = jiffies;
@@ -1007,8 +1008,9 @@ rio_error (struct net_device *dev, int i
/* PCI Error, a catastronphic error related to the bus interface
occurs, set GlobalReset and HostReset to reset. */
if (int_status & HostError) {
- printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
- dev->name, int_status);
+ printk (KERN_ERR "%s: HostError! IntStatus %4.4x. %d
%d %x %x\n",
+ dev->name, int_status, np->cur_tx, np->cur_rx,
+ readl (ioaddr + DMACtrl), readw(ioaddr + IntEnable));
writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
mdelay (500);
}

On Fri, 17 Dec 2004 12:05:21 -0600, Jon Mason <jdmason@gmail.com> wrote:
> It seems to me that the driver does not re-enable interrupts or the
> transmit and receive engines after it resets the adapter because of
> the PCI bus error.
>
> So, I would like to provide you with a patch which will log the state
> of these registers after the adapter reset and during the transmit
> timeout events to dmesg. If you do not have the kernel source
> available, I can try and compile the module for you (it will just take
> a bit longer, as I will have to find the SuSE 9.2 source).
>
> Thanks,
> Jon
>
> On Fri, 17 Dec 2004 18:15:13 +0100, Richard Ems
> <richard.ems@mtg-marinetechnik.de> wrote:
> > Jon Mason wrote:
> > > It seems to me the cause of the tx timeouts is the "HostError", which
> > > is a PCI bus error. This most likely caused the adapter to hang and
> > > then the transmits started timing out.
> > >
> > > As far as I can tell, the dl2k driver code is common between 2.4 and
> > > 2.6. So, some other change in the kernel is causing the driver to
> > > behave differently and expose this problem.
> > >
> > > I am not the maintainer, but I can try to assist you. However, it will
> > > require running debug drivers (as I am not able to find any
> > > documentation on this adapter). If you are not willing or able to do
> > > this, then I would suggest going back to the 2.4 kernel.
> >
> > Ok, yes, I'm willing to try your debug drivers. We'll see if I'm also
> > able ;-)
> >
> > What shall I do?
> >
> > Thanks ,Richard
> >
> > --
> > Richard Ems
> >
> > MTG Marinetechnik GmbH
> > Wandsbeker Königstr. 62
> > 22041 Hamburg
> > Telefon: +49 40 65803 312
> > TeleFax: +49 40 65803 392
> > mail: richard.ems@mtg-marinetechnik.de
> >
> >
>

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--- dl2k.c 2004-09-10 10:46:34.000000000 -0500
+++ /tmp/dl2k.c 2004-12-17 14:37:40.644124080 -0600
@@ -565,8 +565,9 @@ rio_tx_timeout (struct net_device *dev)
{
long ioaddr = dev->base_addr;

- printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
- dev->name, readl (ioaddr + TxStatus));
+ printk (KERN_INFO "%s: Tx timed out (%4.4x) %d %d %x %x\n",
+ dev->name, readl (ioaddr + TxStatus), np->cur_tx, np->cur_rx,
+ readl (ioaddr + DMACtrl), readw(ioaddr + IntEnable));
rio_free_tx(dev, 0);
dev->if_port = 0;
dev->trans_start = jiffies;
@@ -1007,8 +1008,9 @@ rio_error (struct net_device *dev, int i
/* PCI Error, a catastronphic error related to the bus interface
occurs, set GlobalReset and HostReset to reset. */
if (int_status & HostError) {
- printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
- dev->name, int_status);
+ printk (KERN_ERR "%s: HostError! IntStatus %4.4x. %d %d %x %x\n",
+ dev->name, int_status, np->cur_tx, np->cur_rx,
+ readl (ioaddr + DMACtrl), readw(ioaddr + IntEnable));
writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
mdelay (500);
}