Re: [PATCH v10 034/108] KVM: x86/mmu: Add Suppress VE bit to shadow_mmio_{value, mask}

Sean Christopherson
2022-11-28T23:51:18Z

On Thu, Nov 17, 2022, Isaku Yamahata wrote:
> On Wed, Nov 09, 2022 at 11:48:30AM +0000,
> "Huang, Kai" <kai.huang@intel.com> wrote:
>
> > On Sat, 2022-10-29 at 23:22 -0700, isaku.yamahata@intel.com wrote:
> > > From: Isaku Yamahata <isaku.yamahata@intel.com>
> > >
> > > Because TDX will need shadow_mmio_mask to be VMX_SUPPRESS_VE | RWX
> > > shadow_mmio_value to be 0, make VMX EPT case use same value for TDX
> > > shadow_mmio_mask.
> > >
> >
> > TDX need to use different mmio_mask/value doesn't mean they need to be changed
> > for VMX guest. I think the true purpose here is to still be able to use a
> > global shadow_mmio_mask for both TDX and VMX guests. So please explicitly call
> > out.
>
> That's right. With this change, per-VM shadow_mmio_{value, mask} can be avoided.
> The common value can be used for both VMX and TDX.

No, the mask can be global, but the value needs to be per-VM. VMX needs to
generate an EPT misconfig, but TDX needs to generate an EPT violation to get the
automagic #VE reflection.