From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1DD3379C2A for ; Wed, 13 May 2026 20:33:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778704417; cv=none; b=WUnO8VfSGX3vhnxArs0Uji6u816DVeLBMp+M9ZLR8K58EmIX6H6F+sCjg7IQRNBkseTWqlr3WifchyYbVzPHAToK1hq0y0K8frVHy+ej3x9PHj0WSHDTxuGoYyDo/912M/laOCn3FFZhlJcRYR1tBrb5dfrqwW+hzVM6tQjwoHw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778704417; c=relaxed/simple; bh=t7DrBUiucO8P42ebUXthxbTL07z1urjUPXtvf4iIW6M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UJ56jWievTM0ktGrW77uHituWF/8FQp9Tl0XWDvfxMewB+HebUfPa/aLFLxDwRIoF/I4xFjqasT2tJbwS0/dk45HAHn8KoRN7jAz2p2O33ww43c5vqJ74UOR0ukhq3AthnghtL4uUl4WBffYHIW0cYfjwYbfMzWPesZGD8BFFYc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=K2zLTnpR; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="K2zLTnpR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778704416; x=1810240416; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t7DrBUiucO8P42ebUXthxbTL07z1urjUPXtvf4iIW6M=; b=K2zLTnpR7k92F6sDehbSbvuvgT8yTWHRW8gJ9ZMyN1uL2lxtNms+cm71 x36F4u5Ezk15osCxFhTeuSaxwt9dP1wzakGe+KvEK8abbhOnZPZ+Y0ul+ fy1p4vbtXROyZi/yYWkJ4KVmgvoK1IiXPRHWWW7zH4E3EhiHxU5hhTr/7 ZdTOxkR8SSsL72K3TfMSMWbz6OGkBPcLDj0B4CPPQWv+ydKfftuRv3sMG kTGmST0BchLyfi9B0xjpWB1rDbfCk9yrBTgc80niFHaQkXDiu8sSfAu0O ziTQH3Z2FGqmXELXWt0/a3DCedPJYNTxd23N4PLtmWdLB9gWF8VH1IShH w==; X-CSE-ConnectionGUID: VbUUpOLRQsWEy/XQKWOAHg== X-CSE-MsgGUID: xAuYKXMtRNK6mmooAVDoWQ== X-IronPort-AV: E=McAfee;i="6800,10657,11785"; a="79623012" X-IronPort-AV: E=Sophos;i="6.23,233,1770624000"; d="scan'208";a="79623012" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2026 13:33:35 -0700 X-CSE-ConnectionGUID: ciPGxiMPQ5261SxmryPbmQ== X-CSE-MsgGUID: hy8evQcnQjebd8T6GYGxxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,233,1770624000"; d="scan'208";a="238076326" Received: from b04f130c83f2.jf.intel.com ([10.165.154.98]) by orviesa008.jf.intel.com with ESMTP; 13 May 2026 13:33:34 -0700 From: Tim Chen To: Peter Zijlstra , Ingo Molnar , K Prateek Nayak , Vincent Guittot Cc: Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Tim Chen , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , Luo Gengkun , linux-kernel@vger.kernel.org Subject: [Patch v4 03/16] sched/cache: Skip cache-aware scheduling for single-threaded processes Date: Wed, 13 May 2026 13:39:14 -0700 Message-Id: <8a59a13aa58fdb48e410ecb2aabd97fe3ea5d256.1778703694.git.tim.c.chen@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chen Yu For a single thread, the current wakeup path tends to place it on the same LLC where it was previously running with cache-hot data. There is no need to enable cache-aware scheduling for single-threaded processes for the following reasons: 1. Cache-aware scheduling primarily benefits multi-threaded processes where threads share data. Single-threaded processes typically have no inter-thread data sharing and thus gain little. 2. Enabling it incurs the additional overhead of tracking the thread's residency in the LLCs. 3. Bypassing single-threaded processes avoids excessive concentration of such tasks on a single LLC. Nevertheless, this check can be omitted if users explicitly provide hints for such single-threaded workloads where different processes have shared memory, e.g., via prctl() or other interfaces to be added in the future. Tested-by: Tingyin Duan Signed-off-by: Chen Yu Co-developed-by: Tim Chen Signed-off-by: Tim Chen --- kernel/sched/fair.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 808f614fc2d2..df21366ba1ca 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -1384,8 +1384,12 @@ static int llc_id(int cpu) return per_cpu(sd_llc_id, cpu); } -static bool invalid_llc_nr(struct mm_struct *mm, int cpu) +static bool invalid_llc_nr(struct mm_struct *mm, struct task_struct *p, + int cpu) { + if (get_nr_threads(p) <= 1) + return true; + return !fits_capacity((mm->sc_stat.nr_running_avg * cpu_smt_num_threads), per_cpu(sd_llc_size, cpu)); } @@ -1581,7 +1585,7 @@ void account_mm_sched(struct rq *rq, struct task_struct *p, s64 delta_exec) * its preferred state. */ if (epoch - READ_ONCE(mm->sc_stat.epoch) > EPOCH_LLC_AFFINITY_TIMEOUT || - invalid_llc_nr(mm, cpu_of(rq))) { + invalid_llc_nr(mm, p, cpu_of(rq))) { if (mm->sc_stat.cpu != -1) mm->sc_stat.cpu = -1; } @@ -1687,9 +1691,9 @@ static inline void update_avg_scale(u64 *avg, u64 sample) static void task_cache_work(struct callback_head *work) { + int cpu, m_a_cpu = -1, nr_running = 0, curr_cpu; unsigned long next_scan, now = jiffies; struct task_struct *p = current, *cur; - int cpu, m_a_cpu = -1, nr_running = 0; unsigned long curr_m_a_occ = 0; struct mm_struct *mm = p->mm; unsigned long m_a_occ = 0; @@ -1711,6 +1715,14 @@ static void task_cache_work(struct callback_head *work) now + EPOCH_PERIOD)) return; + curr_cpu = task_cpu(p); + if (invalid_llc_nr(mm, p, curr_cpu)) { + if (mm->sc_stat.cpu != -1) + mm->sc_stat.cpu = -1; + + return; + } + if (!zalloc_cpumask_var(&cpus, GFP_KERNEL)) return; @@ -10326,7 +10338,7 @@ static enum llc_mig can_migrate_llc_task(int src_cpu, int dst_cpu, return mig_unrestricted; /* skip cache aware load balance for too many threads */ - if (invalid_llc_nr(mm, dst_cpu)) { + if (invalid_llc_nr(mm, p, dst_cpu)) { if (mm->sc_stat.cpu != -1) mm->sc_stat.cpu = -1; return mig_unrestricted; -- 2.32.0