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X-CSE-ConnectionGUID: JVmGsGTPQmWsn9UmlKGuUw== X-CSE-MsgGUID: MEfToax2RMqG5TA41DkGBA== X-IronPort-AV: E=McAfee;i="6800,10657,11465"; a="55866585" X-IronPort-AV: E=Sophos;i="6.16,240,1744095600"; d="scan'208";a="55866585" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2025 00:12:44 -0700 X-CSE-ConnectionGUID: HjGOjZ05Sou9BY7TtQfcPA== X-CSE-MsgGUID: /QmppINgRhqjZEZzCyDuPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,240,1744095600"; d="scan'208";a="148290800" Received: from allen-sbox.sh.intel.com (HELO [10.239.159.30]) ([10.239.159.30]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2025 00:12:37 -0700 Message-ID: <8b57d3fb-bc0c-4ab6-8a53-22d93718b422@linux.intel.com> Date: Mon, 16 Jun 2025 15:11:37 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 10/25] iommufd/viommu: Add IOMMUFD_CMD_HW_QUEUE_ALLOC ioctl To: Nicolin Chen , jgg@nvidia.com, kevin.tian@intel.com, corbet@lwn.net, will@kernel.org Cc: bagasdotme@gmail.com, robin.murphy@arm.com, joro@8bytes.org, thierry.reding@gmail.com, vdumpa@nvidia.com, jonathanh@nvidia.com, shuah@kernel.org, jsnitsel@redhat.com, nathan@kernel.org, peterz@infradead.org, yi.l.liu@intel.com, mshavit@google.com, praan@google.com, zhangzekun11@huawei.com, iommu@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kselftest@vger.kernel.org, patches@lists.linux.dev, mochs@nvidia.com, alok.a.tiwari@oracle.com, vasant.hegde@amd.com, dwmw2@infradead.org References: <7dfb002613f224f57a069d27e7bf2b306b0a5ba0.1749884998.git.nicolinc@nvidia.com> Content-Language: en-US From: Baolu Lu In-Reply-To: <7dfb002613f224f57a069d27e7bf2b306b0a5ba0.1749884998.git.nicolinc@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/14/25 15:14, Nicolin Chen wrote: > Introduce a new IOMMUFD_CMD_HW_QUEUE_ALLOC ioctl for user space to allocate > a HW QUEUE object for a vIOMMU specific HW-accelerated queue, e.g.: > - NVIDIA's Virtual Command Queue > - AMD vIOMMU's Command Buffer, Event Log Buffers, and PPR Log Buffers > > Since this is introduced with NVIDIA's VCMDQs that access the guest memory > in the physical address space, add an iommufd_hw_queue_alloc_phys() helper > that will create an access object to the queue memory in the IOAS, to avoid > the mappings of the guest memory from being unmapped, during the life cycle > of the HW queue object. > > Reviewed-by: Pranjal Shrivastava > Reviewed-by: Kevin Tian > Signed-off-by: Nicolin Chen Reviewed-by: Lu Baolu