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Thu, 26 Jun 2025 01:27:57 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 26 Jun 2025 01:27:57 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 26 Jun 2025 01:27:57 -0500 Received: from [172.24.227.245] (uda0132425.dhcp.ti.com [172.24.227.245]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55Q6RrJb521448; Thu, 26 Jun 2025 01:27:54 -0500 Message-ID: <8c7f70eb-b64c-408d-816f-9adc997e42ec@ti.com> Date: Thu, 26 Jun 2025 11:57:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/7] arm64: dts: ti: k3-j721s2-main: add DSI & DSI PHY To: Jayesh Choudhary , , CC: , , , , , , , References: <20250624082619.324851-1-j-choudhary@ti.com> <20250624082619.324851-4-j-choudhary@ti.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: <20250624082619.324851-4-j-choudhary@ti.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On 24/06/25 13:56, Jayesh Choudhary wrote: > From: Rahul T R > > Add DT nodes for DPI to DSI Bridge and DSI Phy. > The DSI bridge is Cadence DSI and the PHY is a > Cadence DPHY with TI wrapper. > > Signed-off-by: Rahul T R > [j-choudhary@ti.com: disable dsi and dphy nodes, rename dphy node] > Signed-off-by: Jayesh Choudhary > --- > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 37 ++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > index 83cf0adb2cb7..e17fffc36248 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > @@ -1795,6 +1795,43 @@ main_spi7: spi@2170000 { > status = "disabled"; > }; > > + dphy_tx0: phy@4480000 { > + compatible = "ti,j721e-dphy"; > + reg = <0x0 0x04480000 0x0 0x1000>; > + clocks = <&k3_clks 363 8>, <&k3_clks 363 14>; > + clock-names = "psm", "pll_ref"; > + #phy-cells = <0>; > + power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; > + assigned-clocks = <&k3_clks 363 14>; > + assigned-clock-parents = <&k3_clks 363 15>; > + assigned-clock-rates = <19200000>; > + status = "disabled"; > + }; > + > + dsi0: dsi@4800000 { > + compatible = "ti,j721e-dsi"; > + reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>; > + clocks = <&k3_clks 154 4>, <&k3_clks 154 1>; > + clock-names = "dsi_p_clk", "dsi_sys_clk"; > + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; > + interrupt-parent = <&gic500>; > + interrupts = ; > + phys = <&dphy_tx0>; > + phy-names = "dphy"; > + status = "disabled"; > + > + dsi0_ports: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + }; > + port@1 { > + reg = <1>; > + }; Messed up indentation > + }; > + }; > + > dss: dss@4a00000 { > compatible = "ti,j721e-dss"; > reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ -- Regards Vignesh https://ti.com/opensource