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Mon, 18 Nov 2024 18:55:07 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AIIt6nQ010089 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Nov 2024 18:55:06 GMT Received: from [10.71.108.63] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 18 Nov 2024 10:53:23 -0800 Message-ID: <8d3c2efd-b6c3-4b01-ae01-78460f4e9f26@quicinc.com> Date: Mon, 18 Nov 2024 10:53:16 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/7] clk: qcom: rpmh: Add support for SM8750 rpmh clocks To: Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Trilok Soni , Satya Durga Srinivasu Prabhala , , , , , Bryan O'Donoghue References: <20241112002807.2804021-1-quic_molvera@quicinc.com> <20241112002807.2804021-3-quic_molvera@quicinc.com> <5pgwerxhqhyr2u47grqzgzvvng4rojzq4gozil7vy37bew5pqj@wt676vfjs7bg> Content-Language: en-US From: Melody Olvera In-Reply-To: <5pgwerxhqhyr2u47grqzgzvvng4rojzq4gozil7vy37bew5pqj@wt676vfjs7bg> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: x7H4gC5FBWbnjFVmrT1XC2jv_VGTmafe X-Proofpoint-ORIG-GUID: x7H4gC5FBWbnjFVmrT1XC2jv_VGTmafe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 malwarescore=0 mlxscore=0 phishscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411180155 On 11/15/2024 7:31 AM, Dmitry Baryshkov wrote: > On Mon, Nov 11, 2024 at 04:28:02PM -0800, Melody Olvera wrote: >> From: Taniya Das >> >> Add the RPMH clocks present in SM8750 SoC and fix the match table to >> sort it alphabetically. >> >> Reviewed-by: Bryan O'Donoghue >> Signed-off-by: Taniya Das >> Signed-off-by: Melody Olvera >> --- >> drivers/clk/qcom/clk-rpmh.c | 28 +++++++++++++++++++++++++++- >> 1 file changed, 27 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c >> index eefc322ce367..a3b381e34e48 100644 >> --- a/drivers/clk/qcom/clk-rpmh.c >> +++ b/drivers/clk/qcom/clk-rpmh.c >> @@ -368,6 +368,10 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); >> DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); >> DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); >> >> +DEFINE_CLK_RPMH_VRM(rf_clk3, _a2, "rfclka3", 2); >> +DEFINE_CLK_RPMH_VRM(rf_clk4, _a2, "rfclka4", 2); >> +DEFINE_CLK_RPMH_VRM(rf_clk5, _a2, "rfclka5", 2); > Are the two last clocks defined "for the future platforms"? I'm unsure; I'll let Taniya comment. > >> + >> DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); >> DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); >> DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); >> @@ -807,6 +811,27 @@ static const struct clk_rpmh_desc clk_rpmh_x1e80100 = { >> .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks), >> }; >> >> +static struct clk_hw *sm8750_rpmh_clocks[] = { >> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, >> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, >> + [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, >> + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, >> + [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, >> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, >> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, >> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, >> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, >> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, >> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a2.hw, >> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a2_ao.hw, >> + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, >> +}; >> + >> +static const struct clk_rpmh_desc clk_rpmh_sm8750 = { >> + .clks = sm8750_rpmh_clocks, >> + .num_clks = ARRAY_SIZE(sm8750_rpmh_clocks), >> +}; >> + >> static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, >> void *data) >> { >> @@ -894,6 +919,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { >> { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, >> { .compatible = "qcom,sar2130p-rpmh-clk", .data = &clk_rpmh_sar2130p}, >> { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, >> + { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, >> { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, >> { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, >> { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, >> @@ -909,7 +935,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { >> { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, >> { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, >> { .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650}, >> - { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, > Please don't mix fixes and actual code. I'd suggest splitting sc7280 > move to the separate commit. Bryan O'Donoghue requested we sort these as part of this patch. I don't feel strongly either way, but clear guidance here would be appreciated. Thanks, Melody > >> + { .compatible = "qcom,sm8750-rpmh-clk", .data = &clk_rpmh_sm8750}, >> { .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100}, >> { } >> }; >> -- >> 2.46.1 >>