[PATCH 0/4] Add reset controllers for other TH1520 subsystems

[PATCH 0/4] Add reset controllers for other TH1520 subsystems

[Yao Zi]

TH1520 SoC is split into several subsystems, and each of them comes with
distinct reset controllers. We've already had the one for VO subsystem
documented as "thead,th1520-reset" and supported, and this series adds
support for others, including AO, VI, MISC, AP, DSP and VO.

Note the reset controller for AO subsystem is marked as "reserved" in
devicetree since AON firmware may make use of it and access in Linux
side may cause races.

This series is based on next-20250829, thanks for your time and review.

Yao Zi (4):
  dt-bindings: reset: thead,th1520-reset: Add controllers for more
    subsys
  reset: th1520: Prepare for supporting multiple controllers
  reset: th1520: Support reset controllers in more subsystems
  riscv: dts: thead: Add reset controllers of more subsystems for TH1520

 .../bindings/reset/thead,th1520-reset.yaml    |   8 +-
 arch/riscv/boot/dts/thead/th1520.dtsi         |  37 +
 drivers/reset/reset-th1520.c                  | 835 +++++++++++++++++-
 .../dt-bindings/reset/thead,th1520-reset.h    | 219 ++++-
 4 files changed, 1083 insertions(+), 16 deletions(-)

-- 
2.50.1

[PATCH 1/4] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Yao Zi]

TH1520 SoC is divided into several subsystems, most of them have
distinct reset controllers. Let's document reset controllers other than
the one for VO subsystem and IDs for their reset signals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 .../bindings/reset/thead,th1520-reset.yaml    |   8 +-
 .../dt-bindings/reset/thead,th1520-reset.h    | 219 +++++++++++++++++-
 2 files changed, 223 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
index f2e91d0add7a..7b5053c177fe 100644
--- a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
@@ -16,7 +16,13 @@ maintainers:
 properties:
   compatible:
     enum:
-      - thead,th1520-reset
+      - thead,th1520-reset # Reset controller for VO subsystem
+      - thead,th1520-reset-ao
+      - thead,th1520-reset-ap
+      - thead,th1520-reset-dsp
+      - thead,th1520-reset-misc
+      - thead,th1520-reset-vi
+      - thead,th1520-reset-vp
 
   reg:
     maxItems: 1
diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
index ee799286c175..927e251edfab 100644
--- a/include/dt-bindings/reset/thead,th1520-reset.h
+++ b/include/dt-bindings/reset/thead,th1520-reset.h
@@ -7,11 +7,186 @@
 #ifndef _DT_BINDINGS_TH1520_RESET_H
 #define _DT_BINDINGS_TH1520_RESET_H
 
+/* AO Subsystem */
+#define TH1520_RESET_ID_SYSTEM		0
+#define TH1520_RESET_ID_RTC_APB		1
+#define TH1520_RESET_ID_RTC_REF		2
+#define TH1520_RESET_ID_AOGPIO_DB	3
+#define TH1520_RESET_ID_AOGPIO_APB	4
+#define TH1520_RESET_ID_AOI2C_APB	5
+#define TH1520_RESET_ID_PVT_APB		6
+#define TH1520_RESET_ID_E902_CORE	7
+#define TH1520_RESET_ID_E902_HAD	8
+#define TH1520_RESET_ID_AOTIMER_APB	9
+#define TH1520_RESET_ID_AOTIMER_CORE	10
+#define TH1520_RESET_ID_AOWDT_APB	11
+#define TH1520_RESET_ID_APSYS		12
+#define TH1520_RESET_ID_NPUSYS		13
+#define TH1520_RESET_ID_DDRSYS		14
+#define TH1520_RESET_ID_AXI_AP2CP	15
+#define TH1520_RESET_ID_AXI_CP2AP	16
+#define TH1520_RESET_ID_AXI_CP2SRAM	17
+#define TH1520_RESET_ID_AUDSYS_CORE	18
+#define TH1520_RESET_ID_AUDSYS_IOPMP	19
+#define TH1520_RESET_ID_AUDSYS		20
+#define TH1520_RESET_ID_DSP0		21
+#define TH1520_RESET_ID_DSP1		22
+#define TH1520_RESET_ID_GPU_MODULE	23
+#define TH1520_RESET_ID_VDEC		24
+#define TH1520_RESET_ID_VENC		25
+#define TH1520_RESET_ID_ADC_APB		26
+#define TH1520_RESET_ID_AUDGPIO_DB	27
+#define TH1520_RESET_ID_AUDGPIO_APB	28
+#define TH1520_RESET_ID_AOUART_IF	29
+#define TH1520_RESET_ID_AOUART_APB	30
+#define TH1520_RESET_ID_SRAM_AXI_P0	31
+#define TH1520_RESET_ID_SRAM_AXI_P1	32
+#define TH1520_RESET_ID_SRAM_AXI_P2	33
+#define TH1520_RESET_ID_SRAM_AXI_P3	34
+#define TH1520_RESET_ID_SRAM_AXI_P4	35
+#define TH1520_RESET_ID_SRAM_AXI_CORE	36
+#define TH1520_RESET_ID_SE		37
+
+/* AP Subsystem */
+#define TH1520_RESET_ID_BROM			0
+#define TH1520_RESET_ID_C910_TOP		1
+#define TH1520_RESET_ID_NPU			2
+#define TH1520_RESET_ID_WDT0			3
+#define TH1520_RESET_ID_WDT1			4
+#define TH1520_RESET_ID_C910_C0			5
+#define TH1520_RESET_ID_C910_C1			5
+#define TH1520_RESET_ID_C910_C2			5
+#define TH1520_RESET_ID_C910_C3			5
+#define TH1520_RESET_ID_CHIP_DBG_CORE		6
+#define TH1520_RESET_ID_CHIP_DBG_AXI		7
+#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI	8
+#define TH1520_RESET_ID_AXI4_CPUSYS2_APB	9
+#define TH1520_RESET_ID_X2H_CPUSYS		10
+#define TH1520_RESET_ID_AHB2_CPUSYS		11
+#define TH1520_RESET_ID_APB3_CPUSYS		12
+#define TH1520_RESET_ID_MBOX0_APB		13
+#define TH1520_RESET_ID_MBOX1_APB		14
+#define TH1520_RESET_ID_MBOX2_APB		15
+#define TH1520_RESET_ID_MBOX3_APB		16
+#define TH1520_RESET_ID_TIMER0_APB		17
+#define TH1520_RESET_ID_TIMER0_CORE		18
+#define TH1520_RESET_ID_TIMER1_APB		19
+#define TH1520_RESET_ID_TIMER1_CORE		20
+#define TH1520_RESET_ID_PERISYS_AHB		21
+#define TH1520_RESET_ID_PERISYS_APB1		22
+#define TH1520_RESET_ID_PERISYS_APB2		23
+#define TH1520_RESET_ID_GMAC0_APB		24
+#define TH1520_RESET_ID_GMAC0_AHB		25
+#define TH1520_RESET_ID_GMAC0_CLKGEN		26
+#define TH1520_RESET_ID_GMAC0_AXI		27
+#define TH1520_RESET_ID_UART0_APB		28
+#define TH1520_RESET_ID_UART0_IF		29
+#define TH1520_RESET_ID_UART1_APB		30
+#define TH1520_RESET_ID_UART1_IF		31
+#define TH1520_RESET_ID_UART2_APB		32
+#define TH1520_RESET_ID_UART2_IF		33
+#define TH1520_RESET_ID_UART3_APB		34
+#define TH1520_RESET_ID_UART3_IF		35
+#define TH1520_RESET_ID_UART4_APB		36
+#define TH1520_RESET_ID_UART4_IF		37
+#define TH1520_RESET_ID_UART5_APB		38
+#define TH1520_RESET_ID_UART5_IF		39
+#define TH1520_RESET_ID_QSPI0_IF		40
+#define TH1520_RESET_ID_QSPI0_APB		41
+#define TH1520_RESET_ID_QSPI1_IF		42
+#define TH1520_RESET_ID_QSPI1_APB		43
+#define TH1520_RESET_ID_SPI_IF			44
+#define TH1520_RESET_ID_SPI_APB			45
+#define TH1520_RESET_ID_I2C0_APB		46
+#define TH1520_RESET_ID_I2C0_CORE		47
+#define TH1520_RESET_ID_I2C1_APB		48
+#define TH1520_RESET_ID_I2C1_CORE		49
+#define TH1520_RESET_ID_I2C2_APB		50
+#define TH1520_RESET_ID_I2C2_CORE		51
+#define TH1520_RESET_ID_I2C3_APB		52
+#define TH1520_RESET_ID_I2C3_CORE		53
+#define TH1520_RESET_ID_I2C4_APB		54
+#define TH1520_RESET_ID_I2C4_CORE		55
+#define TH1520_RESET_ID_I2C5_APB		56
+#define TH1520_RESET_ID_I2C5_CORE		57
+#define TH1520_RESET_ID_GPIO0_DB		58
+#define TH1520_RESET_ID_GPIO0_APB		59
+#define TH1520_RESET_ID_GPIO1_DB		60
+#define TH1520_RESET_ID_GPIO1_APB		61
+#define TH1520_RESET_ID_GPIO2_DB		62
+#define TH1520_RESET_ID_GPIO2_APB		63
+#define TH1520_RESET_ID_PWM_COUNTER		64
+#define TH1520_RESET_ID_PWM_APB			65
+#define TH1520_RESET_ID_PADCTRL0_APB		66
+#define TH1520_RESET_ID_CPU2PERI_X2H		67
+#define TH1520_RESET_ID_CPU2AON_X2H		68
+#define TH1520_RESET_ID_AON2CPU_A2X		69
+#define TH1520_RESET_ID_NPUSYS_AXI		70
+#define TH1520_RESET_ID_NPUSYS_AXI_APB		71
+#define TH1520_RESET_ID_CPU2VP_X2P		72
+#define TH1520_RESET_ID_CPU2VI_X2H		73
+#define TH1520_RESET_ID_BMU_AXI			74
+#define TH1520_RESET_ID_BMU_APB			75
+#define TH1520_RESET_ID_DMAC_CPUSYS_AXI		76
+#define TH1520_RESET_ID_DMAC_CPUSYS_AHB		77
+#define TH1520_RESET_ID_SPINLOCK		78
+#define TH1520_RESET_ID_CFG2TEE			79
+#define TH1520_RESET_ID_DSMART			80
+#define TH1520_RESET_ID_GPIO3_DB		81
+#define TH1520_RESET_ID_GPIO3_APB		82
+#define TH1520_RESET_ID_PERI_I2S		83
+#define TH1520_RESET_ID_PERI_APB3		84
+#define TH1520_RESET_ID_PERI2PERI1_APB		85
+#define TH1520_RESET_ID_VPSYS_APB		86
+#define TH1520_RESET_ID_PERISYS_APB4		87
+#define TH1520_RESET_ID_GMAC1_APB		88
+#define TH1520_RESET_ID_GMAC1_AHB		89
+#define TH1520_RESET_ID_GMAC1_CLKGEN		90
+#define TH1520_RESET_ID_GMAC1_AXI		91
+#define TH1520_RESET_ID_GMAC_AXI		92
+#define TH1520_RESET_ID_GMAC_AXI_APB		93
+#define TH1520_RESET_ID_PADCTRL1_APB		94
+#define TH1520_RESET_ID_VOSYS_AXI		95
+#define TH1520_RESET_ID_VOSYS_AXI_APB		96
+#define TH1520_RESET_ID_VOSYS_AXI_X2X		97
+#define TH1520_RESET_ID_MISC2VP_X2X		98
+#define TH1520_RESET_ID_DSPSYS			99
+#define TH1520_RESET_ID_VISYS			100
+#define TH1520_RESET_ID_VOSYS			101
+#define TH1520_RESET_ID_VPSYS			102
+
+/* MISC Subsystem */
+#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN	0
+#define TH1520_RESET_ID_EMMC			1
+#define TH1520_RESET_ID_MISCSYS_AXI		2
+#define TH1520_RESET_ID_MISCSYS_AXI_APB		3
+#define TH1520_RESET_ID_SDIO0			4
+#define TH1520_RESET_ID_SDIO1			5
+#define TH1520_RESET_ID_USB3_APB		6
+#define TH1520_RESET_ID_USB3_PHY		7
+#define TH1520_RESET_ID_USB3_VCC		8
+
+/* VI Subsystem */
+#define TH1520_RESET_ID_ISP0		0
+#define TH1520_RESET_ID_ISP1		1
+#define TH1520_RESET_ID_CSI0_APB	2
+#define TH1520_RESET_ID_CSI1_APB	3
+#define TH1520_RESET_ID_CSI2_APB	4
+#define TH1520_RESET_ID_MIPI_FIFO	5
+#define TH1520_RESET_ID_ISP_VENC_APB	6
+#define TH1520_RESET_ID_VIPRE_APB	7
+#define TH1520_RESET_ID_VIPRE_AXI	8
+#define TH1520_RESET_ID_DW200_APB	9
+#define TH1520_RESET_ID_VISYS3_AXI	10
+#define TH1520_RESET_ID_VISYS2_AXI	11
+#define TH1520_RESET_ID_VISYS1_AXI	12
+#define TH1520_RESET_ID_VISYS_AXI	13
+#define TH1520_RESET_ID_VISYS_APB	14
+#define TH1520_RESET_ID_ISP_VENC_AXI	15
+
+/* VO Subsystem */
 #define TH1520_RESET_ID_GPU		0
 #define TH1520_RESET_ID_GPU_CLKGEN	1
-#define TH1520_RESET_ID_NPU		2
-#define TH1520_RESET_ID_WDT0		3
-#define TH1520_RESET_ID_WDT1		4
 #define TH1520_RESET_ID_DPU_AHB		5
 #define TH1520_RESET_ID_DPU_AXI		6
 #define TH1520_RESET_ID_DPU_CORE	7
@@ -19,5 +194,43 @@
 #define TH1520_RESET_ID_DSI1_APB	9
 #define TH1520_RESET_ID_HDMI		10
 #define TH1520_RESET_ID_HDMI_APB	11
+#define TH1520_RESET_ID_VOAXI		12
+#define TH1520_RESET_ID_VOAXI_APB	13
+#define TH1520_RESET_ID_X2H_DPU_AXI	14
+#define TH1520_RESET_ID_X2H_DPU_AHB	15
+#define TH1520_RESET_ID_X2H_DPU1_AXI	16
+#define TH1520_RESET_ID_X2H_DPU1_AHB	17
+
+/* VP Subsystem */
+#define TH1520_RESET_ID_VPSYS_AXI_APB	0
+#define TH1520_RESET_ID_VPSYS_AXI	1
+#define TH1520_RESET_ID_FCE_APB		2
+#define TH1520_RESET_ID_FCE_CORE	3
+#define TH1520_RESET_ID_FCE_X2X_MASTER	4
+#define TH1520_RESET_ID_FCE_X2X_SLAVE	5
+#define TH1520_RESET_ID_G2D_APB		6
+#define TH1520_RESET_ID_G2D_ACLK	7
+#define TH1520_RESET_ID_G2D_CORE	8
+#define TH1520_RESET_ID_VDEC_APB	9
+#define TH1520_RESET_ID_VDEC_ACLK	10
+#define TH1520_RESET_ID_VDEC_CORE	11
+#define TH1520_RESET_ID_VENC_APB	12
+#define TH1520_RESET_ID_VENC_CORE	13
+
+/* DSP Subsystem */
+#define TH1520_RESET_ID_X2X_DSP1	0
+#define TH1520_RESET_ID_X2X_DSP0	1
+#define TH1520_RESET_ID_X2X_SLAVE_DSP1	2
+#define TH1520_RESET_ID_X2X_SLAVE_DSP0	3
+#define TH1520_RESET_ID_DSP0_CORE	4
+#define TH1520_RESET_ID_DSP0_DEBUG	5
+#define TH1520_RESET_ID_DSP0_APB	6
+#define TH1520_RESET_ID_DSP1_CORE	4
+#define TH1520_RESET_ID_DSP1_DEBUG	5
+#define TH1520_RESET_ID_DSP1_APB	6
+#define TH1520_RESET_ID_DSPSYS_APB	7
+#define TH1520_RESET_ID_AXI4_DSPSYS_SLV	8
+#define TH1520_RESET_ID_AXI4_DSPSYS	9
+#define TH1520_RESET_ID_AXI4_DSP_RS	10
 
 #endif /* _DT_BINDINGS_TH1520_RESET_H */
-- 
2.50.1

[PATCH 2/4] reset: th1520: Prepare for supporting multiple controllers

[Yao Zi]

TH1520 SoC is divided into several subsystems, shipping distinct reset
controllers with similar control logic. Let's make reset signal mapping
a data structure specific to one compatible to prepare for introduction
of more reset controllers in the future.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++-----------
 1 file changed, 30 insertions(+), 12 deletions(-)

diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
index 14d964a9c6b6..2b65a95ed021 100644
--- a/drivers/reset/reset-th1520.c
+++ b/drivers/reset/reset-th1520.c
@@ -29,14 +29,20 @@
 #define TH1520_HDMI_SW_MAIN_RST		BIT(0)
 #define TH1520_HDMI_SW_PRST		BIT(1)
 
+struct th1520_reset_map {
+	u32 bit;
+	u32 reg;
+};
+
 struct th1520_reset_priv {
 	struct reset_controller_dev rcdev;
 	struct regmap *map;
+	const struct th1520_reset_map *resets;
 };
 
-struct th1520_reset_map {
-	u32 bit;
-	u32 reg;
+struct th1520_reset_data {
+	const struct th1520_reset_map *resets;
+	size_t num;
 };
 
 static const struct th1520_reset_map th1520_resets[] = {
@@ -90,7 +96,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev,
 	struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
 	const struct th1520_reset_map *reset;
 
-	reset = &th1520_resets[id];
+	reset = &priv->resets[id];
 
 	return regmap_update_bits(priv->map, reset->reg, reset->bit, 0);
 }
@@ -101,7 +107,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev,
 	struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
 	const struct th1520_reset_map *reset;
 
-	reset = &th1520_resets[id];
+	reset = &priv->resets[id];
 
 	return regmap_update_bits(priv->map, reset->reg, reset->bit,
 				  reset->bit);
@@ -120,11 +126,14 @@ static const struct regmap_config th1520_reset_regmap_config = {
 
 static int th1520_reset_probe(struct platform_device *pdev)
 {
+	const struct th1520_reset_data *data;
 	struct device *dev = &pdev->dev;
 	struct th1520_reset_priv *priv;
 	void __iomem *base;
 	int ret;
 
+	data = device_get_match_data(dev);
+
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
@@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->map))
 		return PTR_ERR(priv->map);
 
-	/* Initialize GPU resets to asserted state */
-	ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
-				 TH1520_GPU_RST_CFG_MASK, 0);
-	if (ret)
-		return ret;
+	if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) {
+		/* Initialize GPU resets to asserted state */
+		ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
+					 TH1520_GPU_RST_CFG_MASK, 0);
+		if (ret)
+			return ret;
+	}
 
 	priv->rcdev.owner = THIS_MODULE;
-	priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets);
+	priv->rcdev.nr_resets = data->num;
 	priv->rcdev.ops = &th1520_reset_ops;
 	priv->rcdev.of_node = dev->of_node;
 
+	priv->resets = data->resets;
+
 	return devm_reset_controller_register(dev, &priv->rcdev);
 }
 
+static const struct th1520_reset_data th1520_reset_data = {
+	.resets = th1520_resets,
+	.num = ARRAY_SIZE(th1520_resets),
+};
+
 static const struct of_device_id th1520_reset_match[] = {
-	{ .compatible = "thead,th1520-reset" },
+	{ .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, th1520_reset_match);
-- 
2.50.1

[PATCH 3/4] reset: th1520: Support reset controllers in more subsystems

[Yao Zi]

Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and
add their reset signal mappings.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/reset/reset-th1520.c | 793 +++++++++++++++++++++++++++++++++++
 1 file changed, 793 insertions(+)

diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
index 2b65a95ed021..f9d87898cf59 100644
--- a/drivers/reset/reset-th1520.c
+++ b/drivers/reset/reset-th1520.c
@@ -11,6 +11,82 @@
 
 #include <dt-bindings/reset/thead,th1520-reset.h>
 
+ /* register offset in RSTGEN_R */
+#define TH1520_BROM_RST_CFG		0x0
+#define TH1520_C910_RST_CFG		0x4
+#define TH1520_CHIP_DBG_RST_CFG		0xc
+#define TH1520_AXI4_CPUSYS2_RST_CFG	0x10
+#define TH1520_X2H_CPUSYS_RST_CFG	0x18
+#define TH1520_AHB2_CPUSYS_RST_CFG	0x1c
+#define TH1520_APB3_CPUSYS_RST_CFG	0x20
+#define TH1520_MBOX0_RST_CFG		0x24
+#define TH1520_MBOX1_RST_CFG		0x28
+#define TH1520_MBOX2_RST_CFG		0x2c
+#define TH1520_MBOX3_RST_CFG		0x30
+#define TH1520_WDT0_RST_CFG		0x34
+#define TH1520_WDT1_RST_CFG		0x38
+#define TH1520_TIMER0_RST_CFG		0x3c
+#define TH1520_TIMER1_RST_CFG		0x40
+#define TH1520_PERISYS_AHB_RST_CFG	0x44
+#define TH1520_PERISYS_APB1_RST_CFG	0x48
+#define TH1520_PERISYS_APB2_RST_CFG	0x4c
+#define TH1520_GMAC0_RST_CFG		0x68
+#define TH1520_UART0_RST_CFG		0x70
+#define TH1520_UART1_RST_CFG		0x74
+#define TH1520_UART2_RST_CFG		0x78
+#define TH1520_UART3_RST_CFG		0x7c
+#define TH1520_UART4_RST_CFG		0x80
+#define TH1520_UART5_RST_CFG		0x84
+#define TH1520_QSPI0_RST_CFG		0x8c
+#define TH1520_QSPI1_RST_CFG		0x90
+#define TH1520_SPI_RST_CFG		0x94
+#define TH1520_I2C0_RST_CFG		0x98
+#define TH1520_I2C1_RST_CFG		0x9c
+#define TH1520_I2C2_RST_CFG		0xa0
+#define TH1520_I2C3_RST_CFG		0xa4
+#define TH1520_I2C4_RST_CFG		0xa8
+#define TH1520_I2C5_RST_CFG		0xac
+#define TH1520_GPIO0_RST_CFG		0xb0
+#define TH1520_GPIO1_RST_CFG		0xb4
+#define TH1520_GPIO2_RST_CFG		0xb8
+#define TH1520_PWM_RST_CFG		0xc0
+#define TH1520_PADCTRL0_APSYS_RST_CFG	0xc4
+#define TH1520_CPU2PERI_X2H_RST_CFG	0xcc
+#define TH1520_CPU2AON_X2H_RST_CFG	0xe4
+#define TH1520_AON2CPU_A2X_RST_CFG	0xfc
+#define TH1520_NPUSYS_AXI_RST_CFG	0x128
+#define TH1520_CPU2VP_X2P_RST_CFG	0x12c
+#define TH1520_CPU2VI_X2H_RST_CFG	0x138
+#define TH1520_BMU_C910_RST_CFG		0x148
+#define TH1520_DMAC_CPUSYS_RST_CFG	0x14c
+#define TH1520_SPINLOCK_RST_CFG		0x178
+#define TH1520_CFG2TEE_X2H_RST_CFG	0x188
+#define TH1520_DSMART_RST_CFG		0x18c
+#define TH1520_GPIO3_RST_CFG		0x1a8
+#define TH1520_I2S_RST_CFG		0x1ac
+#define TH1520_IMG_NNA_RST_CFG		0x1b0
+#define TH1520_PERI_APB3_RST_CFG	0x1dc
+#define TH1520_VP_SUBSYS_RST_CFG	0x1ec
+#define TH1520_PERISYS_APB4_RST_CFG	0x1f8
+#define TH1520_GMAC1_RST_CFG		0x204
+#define TH1520_GMAC_AXI_RST_CFG		0x208
+#define TH1520_PADCTRL1_APSYS_RST_CFG	0x20c
+#define TH1520_VOSYS_AXI_RST_CFG	0x210
+#define TH1520_VOSYS_X2X_RST_CFG	0x214
+#define TH1520_MISC2VP_X2X_RST_CFG	0x218
+#define TH1520_SUBSYS_RST_CFG		0x220
+
+ /* register offset in MISCSYS_REGMAP */
+#define TH1520_EMMC_RST_CFG		0x0
+#define TH1520_MISCSYS_AXI_RST_CFG	0x8
+#define TH1520_SDIO0_RST_CFG		0xc
+#define TH1520_SDIO1_RST_CFG		0x10
+#define TH1520_USB3_DRD_RST_CFG		0x14
+
+ /* register offset in VISYS_REGMAP */
+#define TH1520_VISYS_RST_CFG		0x0
+#define TH1520_VISYS_2_RST_CFG		0x4
+
  /* register offset in VOSYS_REGMAP */
 #define TH1520_GPU_RST_CFG		0x0
 #define TH1520_GPU_RST_CFG_MASK		GENMASK(1, 0)
@@ -18,6 +94,8 @@
 #define TH1520_DSI0_RST_CFG		0x8
 #define TH1520_DSI1_RST_CFG		0xc
 #define TH1520_HDMI_RST_CFG		0x14
+#define TH1520_AXI4_VO_DW_AXI_RST_CFG	0x18
+#define TH1520_X2H_X4_VOSYS_DW_RST_CFG	0x20
 
 /* register values */
 #define TH1520_GPU_SW_GPU_RST		BIT(0)
@@ -29,6 +107,16 @@
 #define TH1520_HDMI_SW_MAIN_RST		BIT(0)
 #define TH1520_HDMI_SW_PRST		BIT(1)
 
+ /* register offset in VPSYS_REGMAP */
+#define TH1520_AXIBUS_RST_CFG		0x0
+#define TH1520_FCE_RST_CFG		0x4
+#define TH1520_G2D_RST_CFG		0x8
+#define TH1520_VDEC_RST_CFG		0xc
+#define TH1520_VENC_RST_CFG		0x10
+
+ /* register offset in DSP_REGMAP */
+#define TH1520_DSPSYS_RST_CFG		0x0
+
 struct th1520_reset_map {
 	u32 bit;
 	u32 reg;
@@ -45,6 +133,539 @@ struct th1520_reset_data {
 	size_t num;
 };
 
+static const struct th1520_reset_map th1520_ap_resets[] = {
+	[TH1520_RESET_ID_BROM] = {
+		.bit = BIT(0),
+		.reg = TH1520_BROM_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_TOP] = {
+		.bit = BIT(0),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_NPU] =  {
+		.bit = BIT(0),
+		.reg = TH1520_IMG_NNA_RST_CFG,
+	},
+	[TH1520_RESET_ID_WDT0] = {
+		.bit = BIT(0),
+		.reg = TH1520_WDT0_RST_CFG,
+	},
+	[TH1520_RESET_ID_WDT1] = {
+		.bit = BIT(0),
+		.reg = TH1520_WDT1_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_C0] = {
+		.bit = BIT(1),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_C1] = {
+		.bit = BIT(2),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_C2] = {
+		.bit = BIT(3),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_C910_C3] = {
+		.bit = BIT(4),
+		.reg = TH1520_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_CHIP_DBG_CORE] = {
+		.bit = BIT(0),
+		.reg = TH1520_CHIP_DBG_RST_CFG,
+	},
+	[TH1520_RESET_ID_CHIP_DBG_AXI] = {
+		.bit = BIT(1),
+		.reg = TH1520_CHIP_DBG_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_AXI4_CPUSYS2_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_CPUSYS2_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_AXI4_CPUSYS2_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_CPUSYS] = {
+		.bit = BIT(0),
+		.reg = TH1520_X2H_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_AHB2_CPUSYS] = {
+		.bit = BIT(0),
+		.reg = TH1520_AHB2_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_APB3_CPUSYS] = {
+		.bit = BIT(0),
+		.reg = TH1520_APB3_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_MBOX0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_MBOX0_RST_CFG,
+	},
+	[TH1520_RESET_ID_MBOX1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_MBOX1_RST_CFG,
+	},
+	[TH1520_RESET_ID_MBOX2_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_MBOX2_RST_CFG,
+	},
+	[TH1520_RESET_ID_MBOX3_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_MBOX3_RST_CFG,
+	},
+	[TH1520_RESET_ID_TIMER0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_TIMER0_RST_CFG,
+	},
+	[TH1520_RESET_ID_TIMER0_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_TIMER0_RST_CFG,
+	},
+	[TH1520_RESET_ID_TIMER1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_TIMER1_RST_CFG,
+	},
+	[TH1520_RESET_ID_TIMER1_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_TIMER1_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERISYS_AHB] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERISYS_AHB_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERISYS_APB1] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERISYS_APB1_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERISYS_APB2] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERISYS_APB2_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GMAC0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC0_AHB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GMAC0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC0_CLKGEN] = {
+		.bit = BIT(2),
+		.reg = TH1520_GMAC0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC0_AXI] = {
+		.bit = BIT(3),
+		.reg = TH1520_GMAC0_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART0_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART0_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART0_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART1_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART1_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART1_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART2_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART2_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART2_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART2_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART3_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART3_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART3_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART3_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART4_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART4_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART4_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART4_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART5_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_UART5_RST_CFG,
+	},
+	[TH1520_RESET_ID_UART5_IF] = {
+		.bit = BIT(1),
+		.reg = TH1520_UART5_RST_CFG,
+	},
+	[TH1520_RESET_ID_QSPI0_IF] = {
+		.bit = BIT(0),
+		.reg = TH1520_QSPI0_RST_CFG,
+	},
+	[TH1520_RESET_ID_QSPI0_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_QSPI0_RST_CFG,
+	},
+	[TH1520_RESET_ID_QSPI1_IF] = {
+		.bit = BIT(0),
+		.reg = TH1520_QSPI1_RST_CFG,
+	},
+	[TH1520_RESET_ID_QSPI1_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_QSPI1_RST_CFG,
+	},
+	[TH1520_RESET_ID_SPI_IF] = {
+		.bit = BIT(0),
+		.reg = TH1520_SPI_RST_CFG,
+	},
+	[TH1520_RESET_ID_SPI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_SPI_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C0_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C0_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C0_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C1_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C1_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C1_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C2_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C2_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C2_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C2_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C3_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C3_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C3_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C3_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C4_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C4_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C4_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C4_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C5_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2C5_RST_CFG,
+	},
+	[TH1520_RESET_ID_I2C5_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_I2C5_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO0_DB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GPIO0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO0_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GPIO0_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO1_DB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GPIO1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO1_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GPIO1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO2_DB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GPIO2_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO2_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GPIO2_RST_CFG,
+	},
+	[TH1520_RESET_ID_PWM_COUNTER] = {
+		.bit = BIT(0),
+		.reg = TH1520_PWM_RST_CFG,
+	},
+	[TH1520_RESET_ID_PWM_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_PWM_RST_CFG,
+	},
+	[TH1520_RESET_ID_PADCTRL0_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_PADCTRL0_APSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_CPU2PERI_X2H] = {
+		.bit = BIT(1),
+		.reg = TH1520_CPU2PERI_X2H_RST_CFG,
+	},
+	[TH1520_RESET_ID_CPU2AON_X2H] = {
+		.bit = BIT(0),
+		.reg = TH1520_CPU2AON_X2H_RST_CFG,
+	},
+	[TH1520_RESET_ID_AON2CPU_A2X] = {
+		.bit = BIT(0),
+		.reg = TH1520_AON2CPU_A2X_RST_CFG,
+	},
+	[TH1520_RESET_ID_NPUSYS_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_NPUSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_NPUSYS_AXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_NPUSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_CPU2VP_X2P] = {
+		.bit = BIT(0),
+		.reg = TH1520_CPU2VP_X2P_RST_CFG,
+	},
+	[TH1520_RESET_ID_CPU2VI_X2H] = {
+		.bit = BIT(0),
+		.reg = TH1520_CPU2VI_X2H_RST_CFG,
+	},
+	[TH1520_RESET_ID_BMU_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_BMU_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_BMU_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_BMU_C910_RST_CFG,
+	},
+	[TH1520_RESET_ID_DMAC_CPUSYS_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_DMAC_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DMAC_CPUSYS_AHB] = {
+		.bit = BIT(1),
+		.reg = TH1520_DMAC_CPUSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_SPINLOCK] = {
+		.bit = BIT(0),
+		.reg = TH1520_SPINLOCK_RST_CFG,
+	},
+	[TH1520_RESET_ID_CFG2TEE] = {
+		.bit = BIT(0),
+		.reg = TH1520_CFG2TEE_X2H_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSMART] = {
+		.bit = BIT(0),
+		.reg = TH1520_DSMART_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO3_DB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GPIO3_RST_CFG,
+	},
+	[TH1520_RESET_ID_GPIO3_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GPIO3_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERI_I2S] = {
+		.bit = BIT(0),
+		.reg = TH1520_I2S_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERI_APB3] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERI_APB3_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERI2PERI1_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_PERI_APB3_RST_CFG,
+	},
+	[TH1520_RESET_ID_VPSYS_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_VP_SUBSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_PERISYS_APB4] = {
+		.bit = BIT(0),
+		.reg = TH1520_PERISYS_APB4_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_GMAC1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC1_AHB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GMAC1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC1_CLKGEN] = {
+		.bit = BIT(2),
+		.reg = TH1520_GMAC1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC1_AXI] = {
+		.bit = BIT(3),
+		.reg = TH1520_GMAC1_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_GMAC_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_GMAC_AXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_GMAC_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_PADCTRL1_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_PADCTRL1_APSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOSYS_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_VOSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOSYS_AXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_VOSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOSYS_AXI_X2X] = {
+		.bit = BIT(0),
+		.reg = TH1520_VOSYS_X2X_RST_CFG,
+	},
+	[TH1520_RESET_ID_MISC2VP_X2X] = {
+		.bit = BIT(0),
+		.reg = TH1520_MISC2VP_X2X_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSPSYS] = {
+		.bit = BIT(0),
+		.reg = TH1520_SUBSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS] = {
+		.bit = BIT(1),
+		.reg = TH1520_SUBSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOSYS] = {
+		.bit = BIT(2),
+		.reg = TH1520_SUBSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VPSYS] = {
+		.bit = BIT(3),
+		.reg = TH1520_SUBSYS_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_misc_resets[] = {
+	[TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = {
+		.bit = BIT(0),
+		.reg = TH1520_EMMC_RST_CFG,
+	},
+	[TH1520_RESET_ID_EMMC] = {
+		.bit = BIT(1),
+		.reg = TH1520_EMMC_RST_CFG,
+	},
+	[TH1520_RESET_ID_MISCSYS_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_MISCSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_MISCSYS_AXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_MISCSYS_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_SDIO0] = {
+		.bit = BIT(0),
+		.reg = TH1520_SDIO0_RST_CFG,
+	},
+	[TH1520_RESET_ID_SDIO1] = {
+		.bit = BIT(1),
+		.reg = TH1520_SDIO1_RST_CFG,
+	},
+	[TH1520_RESET_ID_USB3_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_USB3_DRD_RST_CFG,
+	},
+	[TH1520_RESET_ID_USB3_PHY] = {
+		.bit = BIT(1),
+		.reg = TH1520_USB3_DRD_RST_CFG,
+	},
+	[TH1520_RESET_ID_USB3_VCC] = {
+		.bit = BIT(2),
+		.reg = TH1520_USB3_DRD_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_vi_resets[] = {
+	[TH1520_RESET_ID_ISP0] = {
+		.bit = BIT(0),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_ISP1] = {
+		.bit = BIT(4),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_CSI0_APB] = {
+		.bit = BIT(16),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_CSI1_APB] = {
+		.bit = BIT(17),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_CSI2_APB] = {
+		.bit = BIT(18),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_MIPI_FIFO] = {
+		.bit = BIT(20),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_ISP_VENC_APB] = {
+		.bit = BIT(24),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VIPRE_APB] = {
+		.bit = BIT(28),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VIPRE_AXI] = {
+		.bit = BIT(29),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DW200_APB] = {
+		.bit = BIT(31),
+		.reg = TH1520_VISYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS3_AXI] = {
+		.bit = BIT(8),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS2_AXI] = {
+		.bit = BIT(9),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS1_AXI] = {
+		.bit = BIT(10),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS_AXI] = {
+		.bit = BIT(12),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_VISYS_APB] = {
+		.bit = BIT(16),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+	[TH1520_RESET_ID_ISP_VENC_AXI] = {
+		.bit = BIT(20),
+		.reg = TH1520_VISYS_2_RST_CFG,
+	},
+};
+
 static const struct th1520_reset_map th1520_resets[] = {
 	[TH1520_RESET_ID_GPU] = {
 		.bit = TH1520_GPU_SW_GPU_RST,
@@ -82,6 +703,148 @@ static const struct th1520_reset_map th1520_resets[] = {
 		.bit = TH1520_HDMI_SW_PRST,
 		.reg = TH1520_HDMI_RST_CFG,
 	},
+	[TH1520_RESET_ID_VOAXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_VOAXI_APB] = {
+		.bit = BIT(1),
+		.reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_DPU_AXI] = {
+		.bit = BIT(0),
+		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_DPU_AHB] = {
+		.bit = BIT(1),
+		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_DPU1_AXI] = {
+		.bit = BIT(2),
+		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2H_DPU1_AHB] = {
+		.bit = BIT(3),
+		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_vp_resets[] = {
+	[TH1520_RESET_ID_VPSYS_AXI_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_AXIBUS_RST_CFG,
+	},
+	[TH1520_RESET_ID_VPSYS_AXI] = {
+		.bit = BIT(1),
+		.reg = TH1520_AXIBUS_RST_CFG,
+	},
+	[TH1520_RESET_ID_FCE_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_FCE_RST_CFG,
+	},
+	[TH1520_RESET_ID_FCE_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_FCE_RST_CFG,
+	},
+	[TH1520_RESET_ID_FCE_X2X_MASTER] = {
+		.bit = BIT(4),
+		.reg = TH1520_FCE_RST_CFG,
+	},
+	[TH1520_RESET_ID_FCE_X2X_SLAVE] = {
+		.bit = BIT(5),
+		.reg = TH1520_FCE_RST_CFG,
+	},
+	[TH1520_RESET_ID_G2D_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_G2D_RST_CFG,
+	},
+	[TH1520_RESET_ID_G2D_ACLK] = {
+		.bit = BIT(1),
+		.reg = TH1520_G2D_RST_CFG,
+	},
+	[TH1520_RESET_ID_G2D_CORE] = {
+		.bit = BIT(2),
+		.reg = TH1520_G2D_RST_CFG,
+	},
+	[TH1520_RESET_ID_VDEC_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_VDEC_RST_CFG,
+	},
+	[TH1520_RESET_ID_VDEC_ACLK] = {
+		.bit = BIT(1),
+		.reg = TH1520_VDEC_RST_CFG,
+	},
+	[TH1520_RESET_ID_VDEC_CORE] = {
+		.bit = BIT(2),
+		.reg = TH1520_VDEC_RST_CFG,
+	},
+	[TH1520_RESET_ID_VENC_APB] = {
+		.bit = BIT(0),
+		.reg = TH1520_VENC_RST_CFG,
+	},
+	[TH1520_RESET_ID_VENC_CORE] = {
+		.bit = BIT(1),
+		.reg = TH1520_VENC_RST_CFG,
+	},
+};
+
+static const struct th1520_reset_map th1520_dsp_resets[] = {
+	[TH1520_RESET_ID_X2X_DSP1] = {
+		.bit = BIT(0),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2X_DSP0] = {
+		.bit = BIT(1),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2X_SLAVE_DSP1] = {
+		.bit = BIT(2),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_X2X_SLAVE_DSP0] = {
+		.bit = BIT(3),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP0_CORE] = {
+		.bit = BIT(8),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP0_DEBUG] = {
+		.bit = BIT(9),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP0_APB] = {
+		.bit = BIT(10),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP1_CORE] = {
+		.bit = BIT(12),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP1_DEBUG] = {
+		.bit = BIT(13),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSP1_APB] = {
+		.bit = BIT(14),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_DSPSYS_APB] = {
+		.bit = BIT(16),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_DSPSYS_SLV] = {
+		.bit = BIT(20),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_DSPSYS] = {
+		.bit = BIT(24),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
+	[TH1520_RESET_ID_AXI4_DSP_RS] = {
+		.bit = BIT(26),
+		.reg = TH1520_DSPSYS_RST_CFG,
+	},
 };
 
 static inline struct th1520_reset_priv *
@@ -165,13 +928,43 @@ static int th1520_reset_probe(struct platform_device *pdev)
 	return devm_reset_controller_register(dev, &priv->rcdev);
 }
 
+static const struct th1520_reset_data th1520_ap_reset_data = {
+	.resets = th1520_ap_resets,
+	.num = ARRAY_SIZE(th1520_ap_resets),
+};
+
+static const struct th1520_reset_data th1520_misc_reset_data = {
+	.resets = th1520_misc_resets,
+	.num = ARRAY_SIZE(th1520_misc_resets),
+};
+
+static const struct th1520_reset_data th1520_vi_reset_data = {
+	.resets = th1520_vi_resets,
+	.num = ARRAY_SIZE(th1520_vi_resets),
+};
+
 static const struct th1520_reset_data th1520_reset_data = {
 	.resets = th1520_resets,
 	.num = ARRAY_SIZE(th1520_resets),
 };
 
+static const struct th1520_reset_data th1520_vp_reset_data = {
+	.resets = th1520_vp_resets,
+	.num = ARRAY_SIZE(th1520_vp_resets),
+};
+
+static const struct th1520_reset_data th1520_dsp_reset_data = {
+	.resets = th1520_dsp_resets,
+	.num = ARRAY_SIZE(th1520_dsp_resets),
+};
+
 static const struct of_device_id th1520_reset_match[] = {
+	{ .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data },
+	{ .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data },
+	{ .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data },
 	{ .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
+	{ .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data },
+	{ .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, th1520_reset_match);
-- 
2.50.1

[PATCH 4/4] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

[Yao Zi]

Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
one for AO subsystem is marked as reserved, since it may be used by AON
firmware.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 03f1d7319049..e9fa0df0b56c 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -270,6 +270,12 @@ clint: timer@ffdc000000 {
 					      <&cpu3_intc 3>, <&cpu3_intc 7>;
 		};
 
+		rst_vi: reset-controller@ffe4040100 {
+			compatible = "thead,th1520-reset-vi";
+			reg = <0xff 0xe4040100 0x0 0x8>;
+			#reset-cells = <1>;
+		};
+
 		spi0: spi@ffe700c000 {
 			compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
 			reg = <0xff 0xe700c000 0x0 0x1000>;
@@ -495,6 +501,18 @@ uart2: serial@ffec010000 {
 			status = "disabled";
 		};
 
+		rst_misc: reset-controller@ffec02c000 {
+			compatible = "thead,th1520-reset-misc";
+			reg = <0xff 0xec02c000 0x0 0x18>;
+			#reset-cells = <1>;
+		};
+
+		rst_vp: reset-controller@ffecc30000 {
+			compatible = "thead,th1520-reset-vp";
+			reg = <0xff 0xecc30000 0x0 0x14>;
+			#reset-cells = <1>;
+		};
+
 		clk: clock-controller@ffef010000 {
 			compatible = "thead,th1520-clk-ap";
 			reg = <0xff 0xef010000 0x0 0x1000>;
@@ -502,6 +520,18 @@ clk: clock-controller@ffef010000 {
 			#clock-cells = <1>;
 		};
 
+		rst_ap: reset-controller@ffef014000 {
+			compatible = "thead,th1520-reset-ap";
+			reg = <0xff 0xef014000 0x0 0x1000>;
+			#reset-cells = <1>;
+		};
+
+		rst_dsp: reset-controller@ffef040028 {
+			compatible = "thead,th1520-reset-dsp";
+			reg = <0xff 0xef040028 0x0 0x4>;
+			#reset-cells = <1>;
+		};
+
 		rst: reset-controller@ffef528000 {
 			compatible = "thead,th1520-reset";
 			reg = <0xff 0xef528000 0x0 0x4f>;
@@ -660,6 +690,13 @@ aogpio: gpio-controller@0 {
 			};
 		};
 
+		rst_ao: reset-controller@fffff44000 {
+			compatible = "thead,th1520-reset-ao";
+			reg = <0xff 0xfff44000 0x0 0x2000>;
+			#reset-cells = <1>;
+			status = "reserved";
+		};
+
 		padctrl_aosys: pinctrl@fffff4a000 {
 			compatible = "thead,th1520-pinctrl";
 			reg = <0xff 0xfff4a000 0x0 0x2000>;
-- 
2.50.1

Re: [PATCH 1/4] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Krzysztof Kozlowski]

On Mon, Sep 01, 2025 at 04:23:17AM +0000, Yao Zi wrote:
> +/* VO Subsystem */
>  #define TH1520_RESET_ID_GPU		0
>  #define TH1520_RESET_ID_GPU_CLKGEN	1
> -#define TH1520_RESET_ID_NPU		2
> -#define TH1520_RESET_ID_WDT0		3
> -#define TH1520_RESET_ID_WDT1		4

This is ABI break and deserves explanation and its own patchset.

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Yao Zi]

On Tue, Sep 02, 2025 at 10:27:53AM +0200, Krzysztof Kozlowski wrote:
> On Mon, Sep 01, 2025 at 04:23:17AM +0000, Yao Zi wrote:
> > +/* VO Subsystem */
> >  #define TH1520_RESET_ID_GPU		0
> >  #define TH1520_RESET_ID_GPU_CLKGEN	1
> > -#define TH1520_RESET_ID_NPU		2
> > -#define TH1520_RESET_ID_WDT0		3
> > -#define TH1520_RESET_ID_WDT1		4
> 
> This is ABI break and deserves explanation and its own patchset.

The registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} don't belong
to the VO reset controller (documented as "thead,th1520-reset"), and
thus cannot be implemented by it. They're in fact AP subsystem resets,
which gets supported in Linux with this series.

Is it okay for you to separate a patch to delete these wrong IDs and add
them back for the AP reset controller latter? Anyway, I should have
provided more information about these three resets. Thanks for catching
this.

> Best regards,
> Krzysztof
> 

Best regards,
Yao Zi

Re: [PATCH 3/4] reset: th1520: Support reset controllers in more subsystems

[kernel test robot]

Hi Yao,

kernel test robot noticed the following build warnings:

[auto build test WARNING on pza/reset/next]
[also build test WARNING on next-20250902]
[cannot apply to robh/for-next pza/imx-drm/next linus/master v6.17-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Yao-Zi/dt-bindings-reset-thead-th1520-reset-Add-controllers-for-more-subsys/20250901-122656
base:   https://git.pengutronix.de/git/pza/linux reset/next
patch link:    https://lore.kernel.org/r/20250901042320.22865-4-ziyao%40disroot.org
patch subject: [PATCH 3/4] reset: th1520: Support reset controllers in more subsystems
config: alpha-randconfig-r133-20250902 (https://download.01.org/0day-ci/archive/20250902/202509021804.FXl7up6q-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 8.5.0
reproduce: (https://download.01.org/0day-ci/archive/20250902/202509021804.FXl7up6q-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509021804.FXl7up6q-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/reset/reset-th1520.c:157:10: sparse: sparse: Initializer entry defined twice
   drivers/reset/reset-th1520.c:161:10: sparse:   also defined here
   drivers/reset/reset-th1520.c:808:10: sparse: sparse: Initializer entry defined twice
   drivers/reset/reset-th1520.c:820:10: sparse:   also defined here

vim +157 drivers/reset/reset-th1520.c

   135	
   136	static const struct th1520_reset_map th1520_ap_resets[] = {
   137		[TH1520_RESET_ID_BROM] = {
   138			.bit = BIT(0),
   139			.reg = TH1520_BROM_RST_CFG,
   140		},
   141		[TH1520_RESET_ID_C910_TOP] = {
   142			.bit = BIT(0),
   143			.reg = TH1520_C910_RST_CFG,
   144		},
   145		[TH1520_RESET_ID_NPU] =  {
   146			.bit = BIT(0),
   147			.reg = TH1520_IMG_NNA_RST_CFG,
   148		},
   149		[TH1520_RESET_ID_WDT0] = {
   150			.bit = BIT(0),
   151			.reg = TH1520_WDT0_RST_CFG,
   152		},
   153		[TH1520_RESET_ID_WDT1] = {
   154			.bit = BIT(0),
   155			.reg = TH1520_WDT1_RST_CFG,
   156		},
 > 157		[TH1520_RESET_ID_C910_C0] = {
   158			.bit = BIT(1),
   159			.reg = TH1520_C910_RST_CFG,
   160		},
   161		[TH1520_RESET_ID_C910_C1] = {
   162			.bit = BIT(2),
   163			.reg = TH1520_C910_RST_CFG,
   164		},
   165		[TH1520_RESET_ID_C910_C2] = {
   166			.bit = BIT(3),
   167			.reg = TH1520_C910_RST_CFG,
   168		},
   169		[TH1520_RESET_ID_C910_C3] = {
   170			.bit = BIT(4),
   171			.reg = TH1520_C910_RST_CFG,
   172		},
   173		[TH1520_RESET_ID_CHIP_DBG_CORE] = {
   174			.bit = BIT(0),
   175			.reg = TH1520_CHIP_DBG_RST_CFG,
   176		},
   177		[TH1520_RESET_ID_CHIP_DBG_AXI] = {
   178			.bit = BIT(1),
   179			.reg = TH1520_CHIP_DBG_RST_CFG,
   180		},
   181		[TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = {
   182			.bit = BIT(0),
   183			.reg = TH1520_AXI4_CPUSYS2_RST_CFG,
   184		},
   185		[TH1520_RESET_ID_AXI4_CPUSYS2_APB] = {
   186			.bit = BIT(1),
   187			.reg = TH1520_AXI4_CPUSYS2_RST_CFG,
   188		},
   189		[TH1520_RESET_ID_X2H_CPUSYS] = {
   190			.bit = BIT(0),
   191			.reg = TH1520_X2H_CPUSYS_RST_CFG,
   192		},
   193		[TH1520_RESET_ID_AHB2_CPUSYS] = {
   194			.bit = BIT(0),
   195			.reg = TH1520_AHB2_CPUSYS_RST_CFG,
   196		},
   197		[TH1520_RESET_ID_APB3_CPUSYS] = {
   198			.bit = BIT(0),
   199			.reg = TH1520_APB3_CPUSYS_RST_CFG,
   200		},
   201		[TH1520_RESET_ID_MBOX0_APB] = {
   202			.bit = BIT(0),
   203			.reg = TH1520_MBOX0_RST_CFG,
   204		},
   205		[TH1520_RESET_ID_MBOX1_APB] = {
   206			.bit = BIT(0),
   207			.reg = TH1520_MBOX1_RST_CFG,
   208		},
   209		[TH1520_RESET_ID_MBOX2_APB] = {
   210			.bit = BIT(0),
   211			.reg = TH1520_MBOX2_RST_CFG,
   212		},
   213		[TH1520_RESET_ID_MBOX3_APB] = {
   214			.bit = BIT(0),
   215			.reg = TH1520_MBOX3_RST_CFG,
   216		},
   217		[TH1520_RESET_ID_TIMER0_APB] = {
   218			.bit = BIT(0),
   219			.reg = TH1520_TIMER0_RST_CFG,
   220		},
   221		[TH1520_RESET_ID_TIMER0_CORE] = {
   222			.bit = BIT(1),
   223			.reg = TH1520_TIMER0_RST_CFG,
   224		},
   225		[TH1520_RESET_ID_TIMER1_APB] = {
   226			.bit = BIT(0),
   227			.reg = TH1520_TIMER1_RST_CFG,
   228		},
   229		[TH1520_RESET_ID_TIMER1_CORE] = {
   230			.bit = BIT(1),
   231			.reg = TH1520_TIMER1_RST_CFG,
   232		},
   233		[TH1520_RESET_ID_PERISYS_AHB] = {
   234			.bit = BIT(0),
   235			.reg = TH1520_PERISYS_AHB_RST_CFG,
   236		},
   237		[TH1520_RESET_ID_PERISYS_APB1] = {
   238			.bit = BIT(0),
   239			.reg = TH1520_PERISYS_APB1_RST_CFG,
   240		},
   241		[TH1520_RESET_ID_PERISYS_APB2] = {
   242			.bit = BIT(0),
   243			.reg = TH1520_PERISYS_APB2_RST_CFG,
   244		},
   245		[TH1520_RESET_ID_GMAC0_APB] = {
   246			.bit = BIT(0),
   247			.reg = TH1520_GMAC0_RST_CFG,
   248		},
   249		[TH1520_RESET_ID_GMAC0_AHB] = {
   250			.bit = BIT(1),
   251			.reg = TH1520_GMAC0_RST_CFG,
   252		},
   253		[TH1520_RESET_ID_GMAC0_CLKGEN] = {
   254			.bit = BIT(2),
   255			.reg = TH1520_GMAC0_RST_CFG,
   256		},
   257		[TH1520_RESET_ID_GMAC0_AXI] = {
   258			.bit = BIT(3),
   259			.reg = TH1520_GMAC0_RST_CFG,
   260		},
   261		[TH1520_RESET_ID_UART0_APB] = {
   262			.bit = BIT(0),
   263			.reg = TH1520_UART0_RST_CFG,
   264		},
   265		[TH1520_RESET_ID_UART0_IF] = {
   266			.bit = BIT(1),
   267			.reg = TH1520_UART0_RST_CFG,
   268		},
   269		[TH1520_RESET_ID_UART1_APB] = {
   270			.bit = BIT(0),
   271			.reg = TH1520_UART1_RST_CFG,
   272		},
   273		[TH1520_RESET_ID_UART1_IF] = {
   274			.bit = BIT(1),
   275			.reg = TH1520_UART1_RST_CFG,
   276		},
   277		[TH1520_RESET_ID_UART2_APB] = {
   278			.bit = BIT(0),
   279			.reg = TH1520_UART2_RST_CFG,
   280		},
   281		[TH1520_RESET_ID_UART2_IF] = {
   282			.bit = BIT(1),
   283			.reg = TH1520_UART2_RST_CFG,
   284		},
   285		[TH1520_RESET_ID_UART3_APB] = {
   286			.bit = BIT(0),
   287			.reg = TH1520_UART3_RST_CFG,
   288		},
   289		[TH1520_RESET_ID_UART3_IF] = {
   290			.bit = BIT(1),
   291			.reg = TH1520_UART3_RST_CFG,
   292		},
   293		[TH1520_RESET_ID_UART4_APB] = {
   294			.bit = BIT(0),
   295			.reg = TH1520_UART4_RST_CFG,
   296		},
   297		[TH1520_RESET_ID_UART4_IF] = {
   298			.bit = BIT(1),
   299			.reg = TH1520_UART4_RST_CFG,
   300		},
   301		[TH1520_RESET_ID_UART5_APB] = {
   302			.bit = BIT(0),
   303			.reg = TH1520_UART5_RST_CFG,
   304		},
   305		[TH1520_RESET_ID_UART5_IF] = {
   306			.bit = BIT(1),
   307			.reg = TH1520_UART5_RST_CFG,
   308		},
   309		[TH1520_RESET_ID_QSPI0_IF] = {
   310			.bit = BIT(0),
   311			.reg = TH1520_QSPI0_RST_CFG,
   312		},
   313		[TH1520_RESET_ID_QSPI0_APB] = {
   314			.bit = BIT(1),
   315			.reg = TH1520_QSPI0_RST_CFG,
   316		},
   317		[TH1520_RESET_ID_QSPI1_IF] = {
   318			.bit = BIT(0),
   319			.reg = TH1520_QSPI1_RST_CFG,
   320		},
   321		[TH1520_RESET_ID_QSPI1_APB] = {
   322			.bit = BIT(1),
   323			.reg = TH1520_QSPI1_RST_CFG,
   324		},
   325		[TH1520_RESET_ID_SPI_IF] = {
   326			.bit = BIT(0),
   327			.reg = TH1520_SPI_RST_CFG,
   328		},
   329		[TH1520_RESET_ID_SPI_APB] = {
   330			.bit = BIT(1),
   331			.reg = TH1520_SPI_RST_CFG,
   332		},
   333		[TH1520_RESET_ID_I2C0_APB] = {
   334			.bit = BIT(0),
   335			.reg = TH1520_I2C0_RST_CFG,
   336		},
   337		[TH1520_RESET_ID_I2C0_CORE] = {
   338			.bit = BIT(1),
   339			.reg = TH1520_I2C0_RST_CFG,
   340		},
   341		[TH1520_RESET_ID_I2C1_APB] = {
   342			.bit = BIT(0),
   343			.reg = TH1520_I2C1_RST_CFG,
   344		},
   345		[TH1520_RESET_ID_I2C1_CORE] = {
   346			.bit = BIT(1),
   347			.reg = TH1520_I2C1_RST_CFG,
   348		},
   349		[TH1520_RESET_ID_I2C2_APB] = {
   350			.bit = BIT(0),
   351			.reg = TH1520_I2C2_RST_CFG,
   352		},
   353		[TH1520_RESET_ID_I2C2_CORE] = {
   354			.bit = BIT(1),
   355			.reg = TH1520_I2C2_RST_CFG,
   356		},
   357		[TH1520_RESET_ID_I2C3_APB] = {
   358			.bit = BIT(0),
   359			.reg = TH1520_I2C3_RST_CFG,
   360		},
   361		[TH1520_RESET_ID_I2C3_CORE] = {
   362			.bit = BIT(1),
   363			.reg = TH1520_I2C3_RST_CFG,
   364		},
   365		[TH1520_RESET_ID_I2C4_APB] = {
   366			.bit = BIT(0),
   367			.reg = TH1520_I2C4_RST_CFG,
   368		},
   369		[TH1520_RESET_ID_I2C4_CORE] = {
   370			.bit = BIT(1),
   371			.reg = TH1520_I2C4_RST_CFG,
   372		},
   373		[TH1520_RESET_ID_I2C5_APB] = {
   374			.bit = BIT(0),
   375			.reg = TH1520_I2C5_RST_CFG,
   376		},
   377		[TH1520_RESET_ID_I2C5_CORE] = {
   378			.bit = BIT(1),
   379			.reg = TH1520_I2C5_RST_CFG,
   380		},
   381		[TH1520_RESET_ID_GPIO0_DB] = {
   382			.bit = BIT(0),
   383			.reg = TH1520_GPIO0_RST_CFG,
   384		},
   385		[TH1520_RESET_ID_GPIO0_APB] = {
   386			.bit = BIT(1),
   387			.reg = TH1520_GPIO0_RST_CFG,
   388		},
   389		[TH1520_RESET_ID_GPIO1_DB] = {
   390			.bit = BIT(0),
   391			.reg = TH1520_GPIO1_RST_CFG,
   392		},
   393		[TH1520_RESET_ID_GPIO1_APB] = {
   394			.bit = BIT(1),
   395			.reg = TH1520_GPIO1_RST_CFG,
   396		},
   397		[TH1520_RESET_ID_GPIO2_DB] = {
   398			.bit = BIT(0),
   399			.reg = TH1520_GPIO2_RST_CFG,
   400		},
   401		[TH1520_RESET_ID_GPIO2_APB] = {
   402			.bit = BIT(1),
   403			.reg = TH1520_GPIO2_RST_CFG,
   404		},
   405		[TH1520_RESET_ID_PWM_COUNTER] = {
   406			.bit = BIT(0),
   407			.reg = TH1520_PWM_RST_CFG,
   408		},
   409		[TH1520_RESET_ID_PWM_APB] = {
   410			.bit = BIT(1),
   411			.reg = TH1520_PWM_RST_CFG,
   412		},
   413		[TH1520_RESET_ID_PADCTRL0_APB] = {
   414			.bit = BIT(0),
   415			.reg = TH1520_PADCTRL0_APSYS_RST_CFG,
   416		},
   417		[TH1520_RESET_ID_CPU2PERI_X2H] = {
   418			.bit = BIT(1),
   419			.reg = TH1520_CPU2PERI_X2H_RST_CFG,
   420		},
   421		[TH1520_RESET_ID_CPU2AON_X2H] = {
   422			.bit = BIT(0),
   423			.reg = TH1520_CPU2AON_X2H_RST_CFG,
   424		},
   425		[TH1520_RESET_ID_AON2CPU_A2X] = {
   426			.bit = BIT(0),
   427			.reg = TH1520_AON2CPU_A2X_RST_CFG,
   428		},
   429		[TH1520_RESET_ID_NPUSYS_AXI] = {
   430			.bit = BIT(0),
   431			.reg = TH1520_NPUSYS_AXI_RST_CFG,
   432		},
   433		[TH1520_RESET_ID_NPUSYS_AXI_APB] = {
   434			.bit = BIT(1),
   435			.reg = TH1520_NPUSYS_AXI_RST_CFG,
   436		},
   437		[TH1520_RESET_ID_CPU2VP_X2P] = {
   438			.bit = BIT(0),
   439			.reg = TH1520_CPU2VP_X2P_RST_CFG,
   440		},
   441		[TH1520_RESET_ID_CPU2VI_X2H] = {
   442			.bit = BIT(0),
   443			.reg = TH1520_CPU2VI_X2H_RST_CFG,
   444		},
   445		[TH1520_RESET_ID_BMU_AXI] = {
   446			.bit = BIT(0),
   447			.reg = TH1520_BMU_C910_RST_CFG,
   448		},
   449		[TH1520_RESET_ID_BMU_APB] = {
   450			.bit = BIT(1),
   451			.reg = TH1520_BMU_C910_RST_CFG,
   452		},
   453		[TH1520_RESET_ID_DMAC_CPUSYS_AXI] = {
   454			.bit = BIT(0),
   455			.reg = TH1520_DMAC_CPUSYS_RST_CFG,
   456		},
   457		[TH1520_RESET_ID_DMAC_CPUSYS_AHB] = {
   458			.bit = BIT(1),
   459			.reg = TH1520_DMAC_CPUSYS_RST_CFG,
   460		},
   461		[TH1520_RESET_ID_SPINLOCK] = {
   462			.bit = BIT(0),
   463			.reg = TH1520_SPINLOCK_RST_CFG,
   464		},
   465		[TH1520_RESET_ID_CFG2TEE] = {
   466			.bit = BIT(0),
   467			.reg = TH1520_CFG2TEE_X2H_RST_CFG,
   468		},
   469		[TH1520_RESET_ID_DSMART] = {
   470			.bit = BIT(0),
   471			.reg = TH1520_DSMART_RST_CFG,
   472		},
   473		[TH1520_RESET_ID_GPIO3_DB] = {
   474			.bit = BIT(0),
   475			.reg = TH1520_GPIO3_RST_CFG,
   476		},
   477		[TH1520_RESET_ID_GPIO3_APB] = {
   478			.bit = BIT(1),
   479			.reg = TH1520_GPIO3_RST_CFG,
   480		},
   481		[TH1520_RESET_ID_PERI_I2S] = {
   482			.bit = BIT(0),
   483			.reg = TH1520_I2S_RST_CFG,
   484		},
   485		[TH1520_RESET_ID_PERI_APB3] = {
   486			.bit = BIT(0),
   487			.reg = TH1520_PERI_APB3_RST_CFG,
   488		},
   489		[TH1520_RESET_ID_PERI2PERI1_APB] = {
   490			.bit = BIT(1),
   491			.reg = TH1520_PERI_APB3_RST_CFG,
   492		},
   493		[TH1520_RESET_ID_VPSYS_APB] = {
   494			.bit = BIT(0),
   495			.reg = TH1520_VP_SUBSYS_RST_CFG,
   496		},
   497		[TH1520_RESET_ID_PERISYS_APB4] = {
   498			.bit = BIT(0),
   499			.reg = TH1520_PERISYS_APB4_RST_CFG,
   500		},
   501		[TH1520_RESET_ID_GMAC1_APB] = {
   502			.bit = BIT(0),
   503			.reg = TH1520_GMAC1_RST_CFG,
   504		},
   505		[TH1520_RESET_ID_GMAC1_AHB] = {
   506			.bit = BIT(1),
   507			.reg = TH1520_GMAC1_RST_CFG,
   508		},
   509		[TH1520_RESET_ID_GMAC1_CLKGEN] = {
   510			.bit = BIT(2),
   511			.reg = TH1520_GMAC1_RST_CFG,
   512		},
   513		[TH1520_RESET_ID_GMAC1_AXI] = {
   514			.bit = BIT(3),
   515			.reg = TH1520_GMAC1_RST_CFG,
   516		},
   517		[TH1520_RESET_ID_GMAC_AXI] = {
   518			.bit = BIT(0),
   519			.reg = TH1520_GMAC_AXI_RST_CFG,
   520		},
   521		[TH1520_RESET_ID_GMAC_AXI_APB] = {
   522			.bit = BIT(1),
   523			.reg = TH1520_GMAC_AXI_RST_CFG,
   524		},
   525		[TH1520_RESET_ID_PADCTRL1_APB] = {
   526			.bit = BIT(0),
   527			.reg = TH1520_PADCTRL1_APSYS_RST_CFG,
   528		},
   529		[TH1520_RESET_ID_VOSYS_AXI] = {
   530			.bit = BIT(0),
   531			.reg = TH1520_VOSYS_AXI_RST_CFG,
   532		},
   533		[TH1520_RESET_ID_VOSYS_AXI_APB] = {
   534			.bit = BIT(1),
   535			.reg = TH1520_VOSYS_AXI_RST_CFG,
   536		},
   537		[TH1520_RESET_ID_VOSYS_AXI_X2X] = {
   538			.bit = BIT(0),
   539			.reg = TH1520_VOSYS_X2X_RST_CFG,
   540		},
   541		[TH1520_RESET_ID_MISC2VP_X2X] = {
   542			.bit = BIT(0),
   543			.reg = TH1520_MISC2VP_X2X_RST_CFG,
   544		},
   545		[TH1520_RESET_ID_DSPSYS] = {
   546			.bit = BIT(0),
   547			.reg = TH1520_SUBSYS_RST_CFG,
   548		},
   549		[TH1520_RESET_ID_VISYS] = {
   550			.bit = BIT(1),
   551			.reg = TH1520_SUBSYS_RST_CFG,
   552		},
   553		[TH1520_RESET_ID_VOSYS] = {
   554			.bit = BIT(2),
   555			.reg = TH1520_SUBSYS_RST_CFG,
   556		},
   557		[TH1520_RESET_ID_VPSYS] = {
   558			.bit = BIT(3),
   559			.reg = TH1520_SUBSYS_RST_CFG,
   560		},
   561	};
   562	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 1/4] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Krzysztof Kozlowski]

On 02/09/2025 11:04, Yao Zi wrote:
> On Tue, Sep 02, 2025 at 10:27:53AM +0200, Krzysztof Kozlowski wrote:
>> On Mon, Sep 01, 2025 at 04:23:17AM +0000, Yao Zi wrote:
>>> +/* VO Subsystem */
>>>  #define TH1520_RESET_ID_GPU		0
>>>  #define TH1520_RESET_ID_GPU_CLKGEN	1
>>> -#define TH1520_RESET_ID_NPU		2
>>> -#define TH1520_RESET_ID_WDT0		3
>>> -#define TH1520_RESET_ID_WDT1		4
>>
>> This is ABI break and deserves explanation and its own patchset.
> 
> The registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} don't belong
> to the VO reset controller (documented as "thead,th1520-reset"), and
> thus cannot be implemented by it. They're in fact AP subsystem resets,
> which gets supported in Linux with this series.
> 
> Is it okay for you to separate a patch to delete these wrong IDs and add
> them back for the AP reset controller latter? Anyway, I should have
> provided more information about these three resets. Thanks for catching
> this.

So feels like separate patch dropping these resets with above explanation.

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Philipp Zabel]

On Di, 2025-09-02 at 15:44 +0200, Krzysztof Kozlowski wrote:
> On 02/09/2025 11:04, Yao Zi wrote:
> > On Tue, Sep 02, 2025 at 10:27:53AM +0200, Krzysztof Kozlowski wrote:
> > > On Mon, Sep 01, 2025 at 04:23:17AM +0000, Yao Zi wrote:
> > > > +/* VO Subsystem */
> > > >  #define TH1520_RESET_ID_GPU		0
> > > >  #define TH1520_RESET_ID_GPU_CLKGEN	1
> > > > -#define TH1520_RESET_ID_NPU		2
> > > > -#define TH1520_RESET_ID_WDT0		3
> > > > -#define TH1520_RESET_ID_WDT1		4
> > > 
> > > This is ABI break and deserves explanation and its own patchset.
> > 
> > The registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} don't belong
> > to the VO reset controller (documented as "thead,th1520-reset"), and
> > thus cannot be implemented by it. They're in fact AP subsystem resets,
> > which gets supported in Linux with this series.
> > 
> > Is it okay for you to separate a patch to delete these wrong IDs and add
> > them back for the AP reset controller latter? Anyway, I should have
> > provided more information about these three resets. Thanks for catching
> > this.
> 
> So feels like separate patch dropping these resets with above explanation.

They happen to be reintroduced with exactly the same values, just for
the AP subsystem reset controller:

+/* AP Subsystem */
+#define TH1520_RESET_ID_BROM			0
+#define TH1520_RESET_ID_C910_TOP		1
+#define TH1520_RESET_ID_NPU			2
+#define TH1520_RESET_ID_WDT0			3
+#define TH1520_RESET_ID_WDT1			4
[...]
+/* VO Subsystem */
 #define TH1520_RESET_ID_GPU		0
 #define TH1520_RESET_ID_GPU_CLKGEN	1
-#define TH1520_RESET_ID_NPU		2
-#define TH1520_RESET_ID_WDT0		3
-#define TH1520_RESET_ID_WDT1		4

regards
Philipp

Re: [PATCH 1/4] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Philipp Zabel]

On Mo, 2025-09-01 at 04:23 +0000, Yao Zi wrote:
> TH1520 SoC is divided into several subsystems, most of them have
> distinct reset controllers. Let's document reset controllers other than
> the one for VO subsystem and IDs for their reset signals.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  .../bindings/reset/thead,th1520-reset.yaml    |   8 +-
>  .../dt-bindings/reset/thead,th1520-reset.h    | 219 +++++++++++++++++-
>  2 files changed, 223 insertions(+), 4 deletions(-)
> 
[...]
> diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
> index ee799286c175..927e251edfab 100644
> --- a/include/dt-bindings/reset/thead,th1520-reset.h
> +++ b/include/dt-bindings/reset/thead,th1520-reset.h
> @@ -7,11 +7,186 @@
[...]
> +/* AP Subsystem */
[...]
> +#define TH1520_RESET_ID_C910_C0			5
> +#define TH1520_RESET_ID_C910_C1			5
> +#define TH1520_RESET_ID_C910_C2			5
> +#define TH1520_RESET_ID_C910_C3			5

As the kernel test robot already noticed, this doesn't seem right.

regards
Philipp

Re: [PATCH 3/4] reset: th1520: Support reset controllers in more subsystems

[Maud Spierings]

Hi Yao,

> Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and
> add their reset signal mappings.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---

/* snip */

>  static const struct of_device_id th1520_reset_match[] = {
> +	{ .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data },
> +	{ .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data },
> +	{ .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data },
>  	{ .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
> +	{ .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data },
> +	{ .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data },

I believe these should be alphabetically sorted on compatible name.

>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, th1520_reset_match);
> -- 
> 2.50.1

Kind regards,
Maud

Re: [PATCH 1/4] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Krzysztof Kozlowski]

On 02/09/2025 15:57, Philipp Zabel wrote:
> On Di, 2025-09-02 at 15:44 +0200, Krzysztof Kozlowski wrote:
>> On 02/09/2025 11:04, Yao Zi wrote:
>>> On Tue, Sep 02, 2025 at 10:27:53AM +0200, Krzysztof Kozlowski wrote:
>>>> On Mon, Sep 01, 2025 at 04:23:17AM +0000, Yao Zi wrote:
>>>>> +/* VO Subsystem */
>>>>>  #define TH1520_RESET_ID_GPU		0
>>>>>  #define TH1520_RESET_ID_GPU_CLKGEN	1
>>>>> -#define TH1520_RESET_ID_NPU		2
>>>>> -#define TH1520_RESET_ID_WDT0		3
>>>>> -#define TH1520_RESET_ID_WDT1		4
>>>>
>>>> This is ABI break and deserves explanation and its own patchset.
>>>
>>> The registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} don't belong
>>> to the VO reset controller (documented as "thead,th1520-reset"), and
>>> thus cannot be implemented by it. They're in fact AP subsystem resets,
>>> which gets supported in Linux with this series.
>>>
>>> Is it okay for you to separate a patch to delete these wrong IDs and add
>>> them back for the AP reset controller latter? Anyway, I should have
>>> provided more information about these three resets. Thanks for catching
>>> this.
>>
>> So feels like separate patch dropping these resets with above explanation.
> 
> They happen to be reintroduced with exactly the same values, just for
> the AP subsystem reset controller:

Yes, I noticed, but that's different reset controller, so previous ABI
for that controller stops working. Anyway my comment still stays.
Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

[Yao Zi]

On Tue, Sep 02, 2025 at 03:57:07PM +0200, Philipp Zabel wrote:
> On Mo, 2025-09-01 at 04:23 +0000, Yao Zi wrote:
> > TH1520 SoC is divided into several subsystems, most of them have
> > distinct reset controllers. Let's document reset controllers other than
> > the one for VO subsystem and IDs for their reset signals.
> > 
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  .../bindings/reset/thead,th1520-reset.yaml    |   8 +-
> >  .../dt-bindings/reset/thead,th1520-reset.h    | 219 +++++++++++++++++-
> >  2 files changed, 223 insertions(+), 4 deletions(-)
> > 
> [...]
> > diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
> > index ee799286c175..927e251edfab 100644
> > --- a/include/dt-bindings/reset/thead,th1520-reset.h
> > +++ b/include/dt-bindings/reset/thead,th1520-reset.h
> > @@ -7,11 +7,186 @@
> [...]
> > +/* AP Subsystem */
> [...]
> > +#define TH1520_RESET_ID_C910_C0			5
> > +#define TH1520_RESET_ID_C910_C1			5
> > +#define TH1520_RESET_ID_C910_C2			5
> > +#define TH1520_RESET_ID_C910_C3			5
> 
> As the kernel test robot already noticed, this doesn't seem right.

Yes, this is a copy-paste error. I'll fix it and run static check before
sending v2. Thanks.

> regards
> Philipp

Best regards,
Yao Zi

Re: [PATCH 3/4] reset: th1520: Support reset controllers in more subsystems

[Yao Zi]

On Tue, Sep 02, 2025 at 04:15:08PM +0200, Maud Spierings wrote:
> Hi Yao,
> 
> > Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and
> > add their reset signal mappings.
> > 
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> 
> /* snip */
> 
> >  static const struct of_device_id th1520_reset_match[] = {
> > +	{ .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data },
> > +	{ .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data },
> > +	{ .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data },
> >  	{ .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
> > +	{ .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data },
> > +	{ .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data },
> 
> I believe these should be alphabetically sorted on compatible name.

This is sorted according to the order they appear in the TRM, but yeah
sorting them alphabetically makes more sense. I'll do this in v2.

Thanks,
Yao Zi

> >  	{ /* sentinel */ }
> >  };
> >  MODULE_DEVICE_TABLE(of, th1520_reset_match);
> > -- 
> > 2.50.1
> 
> Kind regards,
> Maud
> 
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