Re: [PATCH v2 1/5] cxl/pci: Add RCH downstream port AER and RAS register discovery

[Terry Bowman <Terry.Bowman@amd.com>]

On 3/24/23 03:53, kernel test robot wrote:

> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <lkp@intel.com>
> | Link: https://lore.kernel.org/oe-kbuild-all/202303241632.HTxJ0yfj-lkp@intel.com/
> 
> sparse warnings: (new ones prefixed by >>)
>>> drivers/cxl/core/regs.c:340:24: sparse: sparse: Using plain integer as NULL pointer
>    drivers/cxl/core/regs.c:345:24: sparse: sparse: Using plain integer as NULL pointer
> 
> vim +340 drivers/cxl/core/regs.c
> 
>    338	
>    339		if (!request_mem_region(map->resource, map->max_size, name))
>  > 340			return 0;
>    341	
>    342		map->base = ioremap(map->resource, map->max_size);
>    343		if (!map->base) {
>    344			release_mem_region(map->resource, map->max_size);
>    345			return 0;
>    346		}
>    347	
>    348		return map->base;
>    349	}
>    350	
> 

Yes, I will change the 0 return value to use NULL instead.

Regards,
Terry