From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22A27C43461 for ; Sun, 13 Sep 2020 20:49:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE41E21655 for ; Sun, 13 Sep 2020 20:49:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725987AbgIMUtc (ORCPT ); Sun, 13 Sep 2020 16:49:32 -0400 Received: from mga02.intel.com ([134.134.136.20]:27723 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725938AbgIMUtb (ORCPT ); Sun, 13 Sep 2020 16:49:31 -0400 IronPort-SDR: NTrregUDSHQUIqScEGZibo63I9i6EHNij60M45vBRHJDVfTTkVc8mcVckyO4ExVZzhYHHQ7DAI 2hMjmXv+eG4w== X-IronPort-AV: E=McAfee;i="6000,8403,9743"; a="146694681" X-IronPort-AV: E=Sophos;i="5.76,423,1592895600"; d="scan'208";a="146694681" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2020 13:49:29 -0700 IronPort-SDR: LrTnDundVGowHR0pcVuwRy/j40/4Lz9JMLUw614H+bYcCMVxBzKSGZb8YBFWD4kgAHNMkMs/TF Z9WJityadbYQ== X-IronPort-AV: E=Sophos;i="5.76,423,1592895600"; d="scan'208";a="330480482" Received: from dhanken-mobl1.amr.corp.intel.com (HELO [10.251.29.129]) ([10.251.29.129]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2020 13:49:29 -0700 Subject: Re: [PATCH v8 1/5] PCI: Conditionally initialize host bridge native_* members From: "Kuppuswamy, Sathyanarayanan" To: Bjorn Helgaas Cc: bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, ashok.raj@intel.com References: <20200910194901.GA808976@bjorn-Precision-5520> Message-ID: <8e9c26fb-97e9-4bda-e374-7c6bea9077eb@linux.intel.com> Date: Sun, 13 Sep 2020 13:49:26 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/10/20 2:00 PM, Kuppuswamy, Sathyanarayanan wrote: > > > On 9/10/20 12:49 PM, Bjorn Helgaas wrote: >> On Fri, Jul 24, 2020 at 08:58:52PM -0700, sathyanarayanan.kuppuswamy@linux.intel.com wrote: >>> From: Kuppuswamy Sathyanarayanan >>> >>> If CONFIG_PCIEPORTBUS is not enabled in kernel then initialing >>> struct pci_host_bridge PCIe specific native_* members to "1" is >>> incorrect. So protect the PCIe specific member initialization >>> with CONFIG_PCIEPORTBUS. >> >> s/initialing/initializing/ > will fix it in next version. >> >>> Signed-off-by: Kuppuswamy Sathyanarayanan >>> --- >>>   drivers/pci/probe.c | 4 +++- >>>   1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >>> index 2f66988cea25..a94b97564ceb 100644 >>> --- a/drivers/pci/probe.c >>> +++ b/drivers/pci/probe.c >>> @@ -588,12 +588,14 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge) >>>        * may implement its own AER handling and use _OSC to prevent the >>>        * OS from interfering. >>>        */ >>> +#ifdef CONFIG_PCIEPORTBUS >>>       bridge->native_aer = 1; >>>       bridge->native_pcie_hotplug = 1; >>> -    bridge->native_shpc_hotplug = 1; >>>       bridge->native_pme = 1; >>>       bridge->native_ltr = 1; >> >> native_ltr isn't dependent on PCIEPORTBUS either, is it?  It's only >> used for ASPM. > Agreed. I was confused due to a comment in include/linux/pci.h > >  unsigned int    native_ltr:1;           /* OS may use PCIe LTR */ Currently there is no code dependency between LTR and CONFIG_PCIEPORTBUS. But I am wondering whether its correct to move LTR code under CONFIG_PCIEPORTBUS?. As per PCIe spec v5.0 sec 7.8.2, LTR is a optional PCIe extended capability. So why is not moved under drivers/pci/pcie/*. What is the criteria for code to be placed under drivers/pci/pcie/* > >> >>>       bridge->native_dpc = 1; >>> +#endif >>> +    bridge->native_shpc_hotplug = 1; >>>       device_initialize(&bridge->dev); >>>   } >>> -- >>> 2.17.1 >>> > -- Sathyanarayanan Kuppuswamy Linux Kernel Developer