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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b87959fc273sm1345590366b.54.2026.01.20.02.59.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Jan 2026 02:59:38 -0800 (PST) Message-ID: <8f7d6dca-d594-413c-81a9-bf51e0d8fdc0@oss.qualcomm.com> Date: Tue, 20 Jan 2026 11:59:36 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] arm64: dts: qcom: milos: Add CCI busses To: Luca Weiss , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20260116-milos-cci-v1-0-28e01128da9c@fairphone.com> <20260116-milos-cci-v1-3-28e01128da9c@fairphone.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260116-milos-cci-v1-3-28e01128da9c@fairphone.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: oj6V-msvSBFhviUG4CImNR4O9-bmP-Dr X-Authority-Analysis: v=2.4 cv=eJMeTXp1 c=1 sm=1 tr=0 ts=696f601c cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=6H0WHjuAAAAA:8 a=KdqX6l0VmMaWkiEhp-gA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-ORIG-GUID: oj6V-msvSBFhviUG4CImNR4O9-bmP-Dr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIwMDA5MSBTYWx0ZWRfXxr3D/Ygx0r0Q GY5MW0rZT+iIaV5D2xCdAFDCejpm5BeON6BcqNI11u+nflskHawAzUZHpcBuD39CmhdR0Kp2nVe sP0s9IotaQ0C4xhk2lryua46K124PKglzoYcvd7vUMBoVXsilePLbmZe5TDy0on1P+EW1kr1dEp /GUbieAqCTyA/8dltc/a3L5J69eA8fUGo8xTVAMAQwHVMQB91RBEtbvTkK4XnT8KnMOnU4zPDZJ KjqFKZ8GAX+vVTQ9dHhqoCVa47G5xe/4aWNmr7XSBNonvc6ShMOHTQVae8U9hK8NqFspOTZuKAa 5htKQEQbeVpe+HcRJ+qIADRhhT5iQOdAJbkoB4SKbLb5TA1mL25A9W32mjaV0whM3l92gigik5d 65kShaEajPvIIo4FnX1ggfYBsncpXNemFclMtSfV2tUpNU9FzzCIOhjD6t+1fOCQ5QHhBDSIExi zh9Jt1UfcQB1kKxZufw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-20_02,2026-01-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 spamscore=0 impostorscore=0 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601200091 On 1/16/26 2:38 PM, Luca Weiss wrote: > Add the nodes and the pinctrl for the CCI I2C busses on the Milos SoC. > > Signed-off-by: Luca Weiss > --- > arch/arm64/boot/dts/qcom/milos.dtsi | 194 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 194 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi > index 58b4c2966df1..c8771beffa9b 100644 > --- a/arch/arm64/boot/dts/qcom/milos.dtsi > +++ b/arch/arm64/boot/dts/qcom/milos.dtsi > @@ -1652,6 +1652,72 @@ videocc: clock-controller@aaf0000 { > #power-domain-cells = <1>; > }; > > + cci0: cci@ac15000 { > + compatible = "qcom,milos-cci", "qcom,msm8996-cci"; > + reg = <0x0 0x0ac15000 0x0 0x1000>; > + interrupts = ; > + power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>; > + clocks = <&camcc CAM_CC_SOC_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_0_CLK>; > + clock-names = "soc_ahb", > + "cpas_ahb", > + "cci"; > + pinctrl-0 = <&cci0_0_default &cci0_1_default>; > + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; > + pinctrl-names = "default", "sleep"; > + status = "disabled"; With the pins moving to the child nodes, we may as well move the disablement there, peeking at the code, I think it should handle it well [...] > camcc: clock-controller@adb0000 { > compatible = "qcom,milos-camcc"; > reg = <0x0 0x0adb0000 0x0 0x40000>; > @@ -1791,6 +1857,134 @@ tlmm: pinctrl@f100000 { > > wakeup-parent = <&pdc>; > > + cci0_0_default: cci0-0-default-state { > + sda-pins { > + pins = "gpio88"; > + function = "cci_i2c_sda"; > + drive-strength = <2>; > + bias-pull-up = <2200>; > + }; It would be fantastic if the GPIOs remained sorted by the GPIO num Konrad