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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>, Avadhut Naik <avadnaik@amd.com>
Cc: yazen.ghannam@amd.com, linux-edac@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] EDAC/mce_amd: Update SMCA bank error descriptions
Date: Mon, 3 Apr 2023 13:24:01 -0400	[thread overview]
Message-ID: <8fe661ef-fa03-5ee9-de57-eec6a5bb7a28@amd.com> (raw)
In-Reply-To: <20230331154412.GBZCb/zO/BGR3a/bVT@fat_crate.local>

On 3/31/23 11:44, Borislav Petkov wrote:
> On Wed, Mar 29, 2023 at 07:22:00PM +0000, Avadhut Naik wrote:
>> diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
>> index cc5c63feb26a..869dcca5e2f4 100644
>> --- a/drivers/edac/mce_amd.c
>> +++ b/drivers/edac/mce_amd.c
>> @@ -192,24 +192,24 @@ static const char * const smca_ls2_mce_desc[] = {
>>  	"A SystemReadDataError error was reported on read data returned from L2 for an SCB store",
>>  	"A SystemReadDataError error was reported on read data returned from L2 for a WCB store",
>>  	"A hardware assertion error was reported",
>> -	"A parity error was detected in an STLF, SCB EMEM entry or SRB store data by any access",
>> +	"A parity error was detected in an STLF, SCB EMEM entry, store data mask or SRB store data by any access",
> 
> I'm assuming that "by any access" is not needed because
> amd_decode_err_code() would say "GEN"-eric for the transaction type
> which is the same thing, basically.
> 

That's fair.

Two (likely weak) arguments for this:
1) Match the wording as closely as possible to the documentation.
2) Folks are likely only looking at the Extended Error Code.

If we deviate to far from the docs, then people will ask us why
Linux says "X" when the docs say "Y". :/

>>  static const char * const smca_if_mce_desc[] = {
>> -	"Op Cache Microtag Probe Port Parity Error",
>> +	"Op Cache Microtag Parity Error",
>>  	"IC Microtag or Full Tag Multi-hit Error",
>>  	"IC Full Tag Parity Error",
>>  	"IC Data Array Parity Error",
>> -	"Decoupling Queue PhysAddr Parity Error",
>> +	"PRQ Parity Error",
>>  	"L0 ITLB Parity Error",
>> -	"L1 ITLB Parity Error",
>> -	"L2 ITLB Parity Error",
>> +	"L1-TLB Parity Error",
>> +	"L2-TLB Parity Error",
>>  	"BPQ Thread 0 Snoop Parity Error",
>>  	"BPQ Thread 1 Snoop Parity Error",
>> -	"L1 BTB Multi-Match Error",
>> -	"L2 BTB Multi-Match Error",
>> +	"BP L1-BTB Multi-Hit Error",
>> +	"BP L2-BTB Multi-Hit Error",
>>  	"L2 Cache Response Poison Error",
>> -	"System Read Data Error",
>> +	"L2 Cache Error Response",
> 
> Hmm, so I don't think we can do that - I'll bet on older Zens, this was
> "System Read Data Error" and on newer it is "L2 Cache Error Response"
> which are not the same thing.
> 
> Right?
> 
> If so, we can't really "update" descriptions like that. If we had to be
> precise, we will have to differentiate by family here. Not sure if we
> care enough but still...
> 

You're right. And that's why we need a new HWID/McaType if the errors codes
change. That's the reason for the other "decoding quirks" set.

In this case, the error is likely the same event. But the description is made
more explicit. Otherwise, we'll need another quirk.

Thanks,
Yazen


      reply	other threads:[~2023-04-03 17:24 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-29 19:22 [PATCH] EDAC/mce_amd: Update SMCA bank error descriptions Avadhut Naik
2023-03-31 15:44 ` Borislav Petkov
2023-04-03 17:24   ` Yazen Ghannam [this message]

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